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JPS5768949A - Buffer memory control system in packet transmission - Google Patents

Buffer memory control system in packet transmission

Info

Publication number
JPS5768949A
JPS5768949A JP55145444A JP14544480A JPS5768949A JP S5768949 A JPS5768949 A JP S5768949A JP 55145444 A JP55145444 A JP 55145444A JP 14544480 A JP14544480 A JP 14544480A JP S5768949 A JPS5768949 A JP S5768949A
Authority
JP
Japan
Prior art keywords
buffer memory
packet
circuit
counters
area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55145444A
Other languages
Japanese (ja)
Other versions
JPH0226920B2 (en
Inventor
Hisashi Morikawa
Taiho Higuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55145444A priority Critical patent/JPS5768949A/en
Publication of JPS5768949A publication Critical patent/JPS5768949A/en
Publication of JPH0226920B2 publication Critical patent/JPH0226920B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer And Data Communications (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Information Transfer Systems (AREA)

Abstract

PURPOSE:To reduce the scale of a control circuit for a buffer memory and to reduce the cost, by commonly using one buffer memory and one set of address counter with a plurality of terminal devices. CONSTITUTION:Data in a plurality of terminal devices 9-1-9-N is made to packet and transmitted to terminal devices 10-1-10-N, then one set of address counters 15, 16 designating write/read address and one buffer memory 13 are provided, and the value of this counter is stored in an area after being split on terminals of a storage circuit 14. The area of the memory 13 is split on terminals and when the counters 15, 16 count up, the content of the circuit 14 is rewritten into a counted-up value, and when the designation of area split on terminals is changed, the content of the area of the circuit 14 is set to the counters 15, 16. The address is designated by counting up from this value set to the counters 15, 16, a packet is inserted to a packet insertion circuit 2, and the reception side picks up the packet at a packet pickup circuit 3.
JP55145444A 1980-10-17 1980-10-17 Buffer memory control system in packet transmission Granted JPS5768949A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55145444A JPS5768949A (en) 1980-10-17 1980-10-17 Buffer memory control system in packet transmission

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55145444A JPS5768949A (en) 1980-10-17 1980-10-17 Buffer memory control system in packet transmission

Publications (2)

Publication Number Publication Date
JPS5768949A true JPS5768949A (en) 1982-04-27
JPH0226920B2 JPH0226920B2 (en) 1990-06-13

Family

ID=15385368

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55145444A Granted JPS5768949A (en) 1980-10-17 1980-10-17 Buffer memory control system in packet transmission

Country Status (1)

Country Link
JP (1) JPS5768949A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2539939A1 (en) * 1983-01-21 1984-07-27 Thomson Csf Mat Tel SWITCHING UNIT FOR PACKAGE DIGITAL DATA SWITCH
JPS6135652A (en) * 1984-07-16 1986-02-20 アメリカン　テレフオン　アンド　テレグラフ　カムパニー Method of controlling data byte
JPS61163754A (en) * 1985-01-14 1986-07-24 Nec Corp Data transmitting and receiving system using plural loops
US4748618A (en) * 1986-05-21 1988-05-31 Bell Communications Research, Inc. Telecommunications interface
JPH01503746A (en) * 1987-05-06 1989-12-14 フィッシャー・アンド・ポーター・カンパニー Improvements regarding packet switching
JPH02501791A (en) * 1987-10-16 1990-06-14 ディジタル　イクイプメント　コーポレーション Computer interconnect couplers for use in data processing equipment clusters
JPH0685842A (en) * 1991-11-29 1994-03-25 American Teleph & Telegr Co <Att> Communication equipment

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49106743A (en) * 1973-02-10 1974-10-09
JPS5199422A (en) * 1975-02-28 1976-09-02 Oki Electric Ind Co Ltd
JPS545637A (en) * 1977-06-15 1979-01-17 Hitachi Ltd Communication control unit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49106743A (en) * 1973-02-10 1974-10-09
JPS5199422A (en) * 1975-02-28 1976-09-02 Oki Electric Ind Co Ltd
JPS545637A (en) * 1977-06-15 1979-01-17 Hitachi Ltd Communication control unit

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2539939A1 (en) * 1983-01-21 1984-07-27 Thomson Csf Mat Tel SWITCHING UNIT FOR PACKAGE DIGITAL DATA SWITCH
JPS6135652A (en) * 1984-07-16 1986-02-20 アメリカン　テレフオン　アンド　テレグラフ　カムパニー Method of controlling data byte
JPS61163754A (en) * 1985-01-14 1986-07-24 Nec Corp Data transmitting and receiving system using plural loops
US4748618A (en) * 1986-05-21 1988-05-31 Bell Communications Research, Inc. Telecommunications interface
JPH01503746A (en) * 1987-05-06 1989-12-14 フィッシャー・アンド・ポーター・カンパニー Improvements regarding packet switching
JPH02501791A (en) * 1987-10-16 1990-06-14 ディジタル　イクイプメント　コーポレーション Computer interconnect couplers for use in data processing equipment clusters
JPH0685842A (en) * 1991-11-29 1994-03-25 American Teleph & Telegr Co <Att> Communication equipment

Also Published As

Publication number Publication date
JPH0226920B2 (en) 1990-06-13

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