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JPS5759242A - Buffer memory circuit of computer output equipment - Google Patents

Buffer memory circuit of computer output equipment

Info

Publication number
JPS5759242A
JPS5759242A JP55133883A JP13388380A JPS5759242A JP S5759242 A JPS5759242 A JP S5759242A JP 55133883 A JP55133883 A JP 55133883A JP 13388380 A JP13388380 A JP 13388380A JP S5759242 A JPS5759242 A JP S5759242A
Authority
JP
Japan
Prior art keywords
counter
data
memory
buffer memory
write
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55133883A
Other languages
Japanese (ja)
Inventor
Toru Asada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Jeol Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Jeol Ltd
Nihon Denshi KK
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jeol Ltd, Nihon Denshi KK, Nippon Telegraph and Telephone Corp filed Critical Jeol Ltd
Priority to JP55133883A priority Critical patent/JPS5759242A/en
Publication of JPS5759242A publication Critical patent/JPS5759242A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)

Abstract

PURPOSE:To enable a general purpose memory having large capacity to be used by providing a write-only count and a read-only counter, and by sending the output of the counters to the address terminal of a buffer memory through switching those outputs in writing-in operation and readout operation. CONSTITUTION:When data is transferred from a computer 1 to an output equipment such as a printer 2, the number of data sent from the computer 1 is counted by a write-only counter in a buffer memory circuit stored with those data, and the number of data read out from a memory 4 is counted by a write-only counter 6. Through a switching circuit 7, the output of the counter 5 is sent to the address assignment terminal of the memory 4 during writing-in operation, and that of the counter is sent during readout operation. Those outputs of the counters 5 and 6 are compared mutually by a comparator 17 and when both are coincident with each other (data in the last address is read out), those counters are cleared. As said buffer memory, a general purpose memory is made usable.
JP55133883A 1980-09-26 1980-09-26 Buffer memory circuit of computer output equipment Pending JPS5759242A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55133883A JPS5759242A (en) 1980-09-26 1980-09-26 Buffer memory circuit of computer output equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55133883A JPS5759242A (en) 1980-09-26 1980-09-26 Buffer memory circuit of computer output equipment

Publications (1)

Publication Number Publication Date
JPS5759242A true JPS5759242A (en) 1982-04-09

Family

ID=15115312

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55133883A Pending JPS5759242A (en) 1980-09-26 1980-09-26 Buffer memory circuit of computer output equipment

Country Status (1)

Country Link
JP (1) JPS5759242A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59121432A (en) * 1982-12-16 1984-07-13 Fujitsu Ltd Print data buffering system of printer
JPH0581165A (en) * 1991-09-19 1993-04-02 Fujitsu Ltd Data transfer circuit
US5780547A (en) * 1991-08-06 1998-07-14 Nippon Gohsei Kagaku Kogyo Kabushiki Kaisha Dispersing stabilizer for suspension polymerization of vinyl chloride

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59121432A (en) * 1982-12-16 1984-07-13 Fujitsu Ltd Print data buffering system of printer
US5780547A (en) * 1991-08-06 1998-07-14 Nippon Gohsei Kagaku Kogyo Kabushiki Kaisha Dispersing stabilizer for suspension polymerization of vinyl chloride
US5977273A (en) * 1991-08-06 1999-11-02 Nippon Gohsei Kagaku Kogyo Kabushiki Kaisha Process for suspension polymerization of vinyl chloride with carboxyl containing polyvinyl-alcohol
JPH0581165A (en) * 1991-09-19 1993-04-02 Fujitsu Ltd Data transfer circuit

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