[go: up one dir, main page]

JPS5733472A - Memory access control system - Google Patents

Memory access control system

Info

Publication number
JPS5733472A
JPS5733472A JP10550480A JP10550480A JPS5733472A JP S5733472 A JPS5733472 A JP S5733472A JP 10550480 A JP10550480 A JP 10550480A JP 10550480 A JP10550480 A JP 10550480A JP S5733472 A JPS5733472 A JP S5733472A
Authority
JP
Japan
Prior art keywords
data
memory
timing
circuit
access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10550480A
Other languages
Japanese (ja)
Inventor
Hidehiko Nishida
Akira Hattori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10550480A priority Critical patent/JPS5733472A/en
Publication of JPS5733472A publication Critical patent/JPS5733472A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To write a new data into an intermediate buffer memory, by varying the timing between the 8-byte storage access and the block storage access type. CONSTITUTION:An access request for storage of 8 bytes of data is given from a central processor not shown in the diagram to a main memory 1. In this case, whether or not the data of the side to receive an access is set to an intermediate memory 2 is indexed through a control table 2-1. If the data is not set to the memory 2, the control signal is applied to a circuit 3 through a selecting circuit 4 to transmit the timing signal successively. With the timing signal, the data is marged 8 with an 8-byte data via a selector 7 to be set to the memory 2. In case the data is already set, the data is sent to a register A5 by the control of a timing circuit A10 and marged 8 via the selector 7 to be set to the memory 2.
JP10550480A 1980-07-31 1980-07-31 Memory access control system Pending JPS5733472A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10550480A JPS5733472A (en) 1980-07-31 1980-07-31 Memory access control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10550480A JPS5733472A (en) 1980-07-31 1980-07-31 Memory access control system

Publications (1)

Publication Number Publication Date
JPS5733472A true JPS5733472A (en) 1982-02-23

Family

ID=14409424

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10550480A Pending JPS5733472A (en) 1980-07-31 1980-07-31 Memory access control system

Country Status (1)

Country Link
JP (1) JPS5733472A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6330670U (en) * 1986-08-13 1988-02-29
JPH0452666U (en) * 1990-09-10 1992-05-06
US5361342A (en) * 1990-07-27 1994-11-01 Fujitsu Limited Tag control system in a hierarchical memory control system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6330670U (en) * 1986-08-13 1988-02-29
US5361342A (en) * 1990-07-27 1994-11-01 Fujitsu Limited Tag control system in a hierarchical memory control system
JPH0452666U (en) * 1990-09-10 1992-05-06

Similar Documents

Publication Publication Date Title
EP0267612A3 (en) Timer/counter using a register block
JPS57105879A (en) Control system for storage device
JPS5733472A (en) Memory access control system
JPS57105877A (en) Stack memory device
JPS5719857A (en) Data compression storage device
JPS57191764A (en) Storage device
JPS5750378A (en) Control system of data processor
JPS576927A (en) Address allotting system
JPS5533282A (en) Buffer control system
JPS5482103A (en) Storage exchange system
JPS56146344A (en) Terminal control device
JPS56149626A (en) Channel device
JPS5491028A (en) Memory control system of multiprocessor system
JPS55157056A (en) Disc cash control system
JPS6419457A (en) Memory device
JPS56143036A (en) Response synchronizing system
JPS56168251A (en) Data transfer buffer system
JPS5712469A (en) Buffer memory control system
JPS576967A (en) Data transfer system
JPS5798051A (en) Memory system of scan in/out data
JPS5759233A (en) Signal transmitting circuit
JPS57137938A (en) Data processor
JPS5475231A (en) Buffer memory control system
JPS56168256A (en) Data processor
JPS5614358A (en) Operation log storing system