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JPS5759233A - Signal transmitting circuit - Google Patents

Signal transmitting circuit

Info

Publication number
JPS5759233A
JPS5759233A JP55134296A JP13429680A JPS5759233A JP S5759233 A JPS5759233 A JP S5759233A JP 55134296 A JP55134296 A JP 55134296A JP 13429680 A JP13429680 A JP 13429680A JP S5759233 A JPS5759233 A JP S5759233A
Authority
JP
Japan
Prior art keywords
circuit
received data
address
signal transmitting
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55134296A
Other languages
Japanese (ja)
Inventor
Norihiko Sugimoto
Ikuro Masuda
Nobuhiro Hamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP55134296A priority Critical patent/JPS5759233A/en
Publication of JPS5759233A publication Critical patent/JPS5759233A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer And Data Communications (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE:To realize a computer system with high processing performance by providing a signal transmitting circuit with an address discriminating function, a temporary storing function, a series-parallel converting function, etc. and reducing the time required for data transfer. CONSTITUTION:A signal transmitting circuit 11 which transmits a signal in a block unit is provided with a parallel-series converting circuit for transmission, an address discriminating circuit 39 which discriminates whether the address of received data indicates the signal transmitting circuit or not during reception, and a buffer register 42 which divides one block of the received data and stores the constant signal length temporarily. Further, an error discriminating circuit which discriminates the occurrence of an error by the constant signal length, a series-parallel converting circuit, and a memory control circuit which controls signal transfer control are provided. Then, when the address of the received data is coincident and the received data is normal, the received data is transferred to a memory.
JP55134296A 1980-09-29 1980-09-29 Signal transmitting circuit Pending JPS5759233A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55134296A JPS5759233A (en) 1980-09-29 1980-09-29 Signal transmitting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55134296A JPS5759233A (en) 1980-09-29 1980-09-29 Signal transmitting circuit

Publications (1)

Publication Number Publication Date
JPS5759233A true JPS5759233A (en) 1982-04-09

Family

ID=15124960

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55134296A Pending JPS5759233A (en) 1980-09-29 1980-09-29 Signal transmitting circuit

Country Status (1)

Country Link
JP (1) JPS5759233A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62220048A (en) * 1986-03-20 1987-09-28 Fujitsu Ltd Packet buffer automatic reuse method
JPS63226762A (en) * 1987-03-16 1988-09-21 Hitachi Ltd Data processing system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5342602A (en) * 1976-09-30 1978-04-18 Fujitsu Ltd Transmission control system
JPS5477040A (en) * 1977-12-02 1979-06-20 Hitachi Ltd Data transmitter

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5342602A (en) * 1976-09-30 1978-04-18 Fujitsu Ltd Transmission control system
JPS5477040A (en) * 1977-12-02 1979-06-20 Hitachi Ltd Data transmitter

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62220048A (en) * 1986-03-20 1987-09-28 Fujitsu Ltd Packet buffer automatic reuse method
JPS63226762A (en) * 1987-03-16 1988-09-21 Hitachi Ltd Data processing system

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