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JPS5460833A - Buffer memory system - Google Patents

Buffer memory system

Info

Publication number
JPS5460833A
JPS5460833A JP12802577A JP12802577A JPS5460833A JP S5460833 A JPS5460833 A JP S5460833A JP 12802577 A JP12802577 A JP 12802577A JP 12802577 A JP12802577 A JP 12802577A JP S5460833 A JPS5460833 A JP S5460833A
Authority
JP
Japan
Prior art keywords
block
buffer memory
control
main
memories
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12802577A
Other languages
Japanese (ja)
Other versions
JPS6029135B2 (en
Inventor
Naoya Ono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP52128025A priority Critical patent/JPS6029135B2/en
Publication of JPS5460833A publication Critical patent/JPS5460833A/en
Publication of JPS6029135B2 publication Critical patent/JPS6029135B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To hold the necessary information in a high probability with a small amount of the secondary buffer memory by allotting in preference the blocks in the secondary buffer memory to either one of the plural sets of the main buffer memory.
CONSTITUTION: The following units are provided: 1st and 2nd set associative system buffer memories to hold part of the block on the main memory; 1st control table 2 to control the address of the block which is presently stored in the 1st buffer memory; and main control table 4 to control the address of the block which is stored in the 2nd buffer memory. Furthermore, replacement control part is provided to control table 4 to hold the information concerning how to give an access to each block in pulural sets corresponding to both memories. Then comparator circuit 3 is connected to replacement control circuit 6 to decide to which block of the both memories the block on the main memory should be allotted based on the information of table 4
COPYRIGHT: (C)1979,JPO&Japio
JP52128025A 1977-10-24 1977-10-24 buffer memory system Expired JPS6029135B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP52128025A JPS6029135B2 (en) 1977-10-24 1977-10-24 buffer memory system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52128025A JPS6029135B2 (en) 1977-10-24 1977-10-24 buffer memory system

Publications (2)

Publication Number Publication Date
JPS5460833A true JPS5460833A (en) 1979-05-16
JPS6029135B2 JPS6029135B2 (en) 1985-07-09

Family

ID=14974620

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52128025A Expired JPS6029135B2 (en) 1977-10-24 1977-10-24 buffer memory system

Country Status (1)

Country Link
JP (1) JPS6029135B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07271672A (en) * 1994-03-30 1995-10-20 Toshiba Corp Multi-way set associative cash system
WO1998019242A1 (en) * 1996-10-30 1998-05-07 Hitachi, Ltd. Data processor and data processing system
JP2016130893A (en) * 2015-01-13 2016-07-21 富士通株式会社 Cache control method and cache controller

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6398898U (en) * 1986-12-19 1988-06-27

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07271672A (en) * 1994-03-30 1995-10-20 Toshiba Corp Multi-way set associative cash system
WO1998019242A1 (en) * 1996-10-30 1998-05-07 Hitachi, Ltd. Data processor and data processing system
US6351788B1 (en) * 1996-10-30 2002-02-26 Hitachi, Ltd. Data processor and data processing system
JP2016130893A (en) * 2015-01-13 2016-07-21 富士通株式会社 Cache control method and cache controller

Also Published As

Publication number Publication date
JPS6029135B2 (en) 1985-07-09

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