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JPS5667428A - Input and output interface - Google Patents

Input and output interface

Info

Publication number
JPS5667428A
JPS5667428A JP14399179A JP14399179A JPS5667428A JP S5667428 A JPS5667428 A JP S5667428A JP 14399179 A JP14399179 A JP 14399179A JP 14399179 A JP14399179 A JP 14399179A JP S5667428 A JPS5667428 A JP S5667428A
Authority
JP
Japan
Prior art keywords
external device
cpu
information
retrial
interface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14399179A
Other languages
Japanese (ja)
Inventor
Makoto Matsuhashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP14399179A priority Critical patent/JPS5667428A/en
Publication of JPS5667428A publication Critical patent/JPS5667428A/en
Pending legal-status Critical Current

Links

Landscapes

  • Retry When Errors Occur (AREA)

Abstract

PURPOSE: To increase the usage efficiency of device, by retrying an external device based on the stored information when a failure is produced in the external device, through the storage of the information to the interface, if access is made from a CPU to the external device.
CONSTITUTION: An input and output interface 11 is connected between a CPU and an external device, and a data transfer section 12 and a retrial control section 13 are provided at this interface 11. Further, when the external device is accessed from a CPU, the output information from a CPU is temporarily stored in various registers 19 in the control section 13, the status from the external device is analyzed at a problem analysis circuit 17 to discriminate whether or not the result of execution of the external device is normal, and retrial control is made at the retrial discrimination control circuit 16 to the external device, based on the information stored in the register 19 when a failure is taken place.
COPYRIGHT: (C)1981,JPO&Japio
JP14399179A 1979-11-07 1979-11-07 Input and output interface Pending JPS5667428A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14399179A JPS5667428A (en) 1979-11-07 1979-11-07 Input and output interface

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14399179A JPS5667428A (en) 1979-11-07 1979-11-07 Input and output interface

Publications (1)

Publication Number Publication Date
JPS5667428A true JPS5667428A (en) 1981-06-06

Family

ID=15351758

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14399179A Pending JPS5667428A (en) 1979-11-07 1979-11-07 Input and output interface

Country Status (1)

Country Link
JP (1) JPS5667428A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57212516A (en) * 1981-06-25 1982-12-27 Fujitsu Ltd Retry controlling method of data transfer between devices

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57212516A (en) * 1981-06-25 1982-12-27 Fujitsu Ltd Retry controlling method of data transfer between devices

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