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JPS57159348A - Microprogram control system - Google Patents

Microprogram control system

Info

Publication number
JPS57159348A
JPS57159348A JP4489181A JP4489181A JPS57159348A JP S57159348 A JPS57159348 A JP S57159348A JP 4489181 A JP4489181 A JP 4489181A JP 4489181 A JP4489181 A JP 4489181A JP S57159348 A JPS57159348 A JP S57159348A
Authority
JP
Japan
Prior art keywords
exceptional
entry
processing
routine
normal routine
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4489181A
Other languages
Japanese (ja)
Other versions
JPS6141421B2 (en
Inventor
Hiroshi Takada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP4489181A priority Critical patent/JPS57159348A/en
Publication of JPS57159348A publication Critical patent/JPS57159348A/en
Publication of JPS6141421B2 publication Critical patent/JPS6141421B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/28—Enhancement of operational speed, e.g. by using several microcontrol devices operating in parallel

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To improve the execution speed, by executing exceptional processing with an exceptional processing entry in pair with a normal routine, when an exceptional state is generated in executing the processing corresponding to a macroinstruction. CONSTITUTION:A control memory 5 instructs a microprogram corresponding to a macroinstruction with a normal routine entry and also instructs an exceptional processing routine corresponding to the exceptional processing entry. At least, one bit in access address information to the memory 5 from an output with an exceptional detection circuit 3 is set or reset. An exceptional entry is accessed in place of a normal routine entry at the presence of the exceptional state and branched into the corresponding exceptional processing routine and the access address information accessing the normal routine entry is stacked to an address stack section 6.
JP4489181A 1981-03-27 1981-03-27 Microprogram control system Granted JPS57159348A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4489181A JPS57159348A (en) 1981-03-27 1981-03-27 Microprogram control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4489181A JPS57159348A (en) 1981-03-27 1981-03-27 Microprogram control system

Publications (2)

Publication Number Publication Date
JPS57159348A true JPS57159348A (en) 1982-10-01
JPS6141421B2 JPS6141421B2 (en) 1986-09-16

Family

ID=12704098

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4489181A Granted JPS57159348A (en) 1981-03-27 1981-03-27 Microprogram control system

Country Status (1)

Country Link
JP (1) JPS57159348A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59188745A (en) * 1983-04-08 1984-10-26 Nec Corp Exception detecting system
JPS63147236A (en) * 1986-12-10 1988-06-20 Nec Corp Information processor

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5242339A (en) * 1975-09-30 1977-04-01 Nec Corp Micro instruction address production system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5242339A (en) * 1975-09-30 1977-04-01 Nec Corp Micro instruction address production system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59188745A (en) * 1983-04-08 1984-10-26 Nec Corp Exception detecting system
JPH0441377B2 (en) * 1983-04-08 1992-07-08 Nippon Electric Co
JPS63147236A (en) * 1986-12-10 1988-06-20 Nec Corp Information processor

Also Published As

Publication number Publication date
JPS6141421B2 (en) 1986-09-16

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