JPH0441377B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a microprogram control method for exception detection in an information processing device, and particularly to its data check and branch control method.

(Prior Art) Conventionally, this type of microprogram control type information processing apparatus has a central processing unit 100 as shown in FIG.
, a control storage address adder 230, a control storage address selector 240, and a working register 30.
0, logic operation circuit 310, data check circuit 320, exception flag 331, and zero flag 33
2, a flag register 330 consisting of a negative flag 333, and a flag selector 340. In the above configuration, the microinstruction of the contents of the control memory 200 at the address indicated by the control memory address register 220 is transferred to and stored in the control memory register 210, and controls the operation of each part within the central processing unit 100.

A microinstruction stored in control storage register 210 is normally transferred to control storage address register 2 using control storage address adder 230.
1 is added to the contents of 20 and controlled to be stored again in the control storage address register 220 through the control storage address selector 240. That is,
By the above operation, the microinstructions at consecutive addresses in the control memory 200 are executed.

If the microinstruction stored in the control storage register 210 is a conditional branch instruction, the data for determining the condition is stored in the working register 300;
A logical operation circuit 310 performs a logical operation, and the result is set to a zero flag 332 in a flag register 330.
and a negative flag 333, select a 1-bit or 2-bit flag by the flag selector 340 so that the desired conditional branch can be performed, and select 1 or 2 bits of the control storage address register 220 through the control storage address selector 240. instructs you to replace it with That is, if the selected flag is 1 bit, a conditional branch is executed in 2 directions, and if it is 2 bits, a conditional branch is executed in 4 directions.

If the microinstruction stored in the control storage register 210 is an exception check instruction, the data to be checked for an exception is stored in the working register 300, the data check circuit 320 performs the exception check, and the result is stored in the flag register 330. The internal error flag 331 is set. Therefore,
A flag is selected by the flag selector 340 and instructed to be replaced with one bit of the contents of the control storage address register 220 through the control address selector 240. In other words, depending on the presence or absence of exceptions,
A two-way conditional branch is executed.

In the information processing device according to the above-mentioned conventional technology, data requires different processing depending on whether the data value is positive, zero, or negative, and if it is necessary to check for exceptions, an 8-bit check is performed using a 3-bit test.
If a way branch is executed using one microinstruction, eight steps of microinstructions are required. In reality, it is necessary in four cases: positive without exception, zero without exception, negative without exception, and with exception, which has the disadvantage that the four steps are wasted. Furthermore, if exception checking and condition determination are separated, performance deteriorates, and the prior art has the disadvantage that either a decrease in control memory usage efficiency or a decrease in performance is unavoidable.

(Objective of the Invention) The object of the present invention is to detect an exception at the same time when performing a condition judgment that includes a combination that cannot occur, and to change the above condition judgment to a condition that cannot occur due to the detection of the exception. It is an object of the present invention to provide an exception detection method that eliminates the above-mentioned drawbacks and has high control memory usage efficiency and performance.

(Structure of the Invention) The exception detection method according to the present invention includes a working register, a logic operation circuit, a plurality of flag registers,
It is realized by comprising a data check circuit, a flag change circuit, and a flag selector, and is constructed using a microprogram control system.

The working register is for storing data that requires exception detection and condition determination.

The logical operation circuit is for performing logical operations on data.

The plurality of flag registers are for displaying the results of logical operations.

The data check circuit is for detecting data exceptions.

The flag change circuit is for changing a combination of a plurality of flag registers to an originally impossible combination when an exception is detected.

The flag selector is for selecting a branch mode of a conditional branch according to the display in the flag register.

(Embodiment) In FIG. 2 showing an embodiment of the present invention, the information processing device of the present invention includes a control memory 200 and a control memory register 210 inside the central processing unit 100.
Consists of a control memory address register 220, a control memory address adder 230, a control memory address selector 240, a working register 300, a logic operation circuit 310, a data check circuit 320, a zero flag 332, and a negative flag 333. It is composed of a flag register 330, a flag selector 340, and a flag change circuit 350.

In the above configuration, the microinstruction stored at the internal address of the control memory 200 specified by the control memory address register 22 is transferred to and stored in the control memory register 210, and controls the operation of each internal part of the central processing unit 100. .

In the normal case, microinstructions stored in control storage register 210 are transferred to control storage address register 210 using control storage address adder 230.
1 is added to the contents of 0, and the control memory address register 22 is added to the control memory address register 22 through the control memory address selector 240.
Control so that it is stored at 0. That is, microinstructions at consecutive addresses stored in control memory 200 are executed.

In case of conditional branch, control storage register 2
20 stores data to be subjected to condition determination in a working register 300, performs a logical operation by a logical operation circuit 310,
The calculation result is stored in a zero flag 332 and a negative flag 333 inside the flag register 330. Therefore, in order to perform the desired conditional branch, the flag selector 340 selects a 1-bit or 2-bit flag, and the control storage address selector 2 selects a 1-bit or 2-bit flag.
40 instructs to replace one or two bits of the control storage address register 220. That is, if the selected flag is 1 bit, a 2-way conditional branch is executed, and if it is 2 bits, a 4-way conditional branch is executed. In this case, the zero flag 332 and the negative flag 333 are not set at the same time as in the conventional example.

Next, consider data that requires exception checking and requires different processing depending on whether the data value is positive, zero, or negative. In the case of a conditional branch with an exception check that simultaneously performs an exception check and a conditional determination of whether the data value is positive, zero, or negative, the exception check and conditional determination should be performed by a microinstruction stored in the control storage register 210. It stores the data in the working register 300, instructs the logic operation circuit 310 to perform a logical operation, and also controls the data check circuit 320 to instruct exception checking of the contents of the working register 300. If there is no exception, the data check circuit 320 outputs a logic value of 0, so the flag change circuit 350 transfers the flag value output from the logic operation circuit 310 to the flag register 330 as is.

If an exception exists, the data check circuit 320 outputs a logic value of 1, so the flag change circuit 350 changes the values of all bits to 1 and sets the flag regardless of the value of the flag output from the logic operation circuit 310. Transfer to register 330. The microinstruction stores the value transferred to flag register 330;
The flag selector 340 selects two bits, the zero flag 332 and the negative flag 333, and the control storage address selector 240 replaces them with the two bits of the control storage address register 220. In other words, conditional branching in four directions is executed. In this case, there are four cases: positive without exception, zero without exception, negative without exception, and with exception.

As can be understood from the above description, compared to the prior art, the embodiment according to the present invention requires half the amount of hardware for control storage if the performance is the same, and doubles the performance if the amount of control storage is the same. Note that in the above explanation, an example of a zero flag and a negative flag was shown, but if there are multiple flags that have an impossible combination,
Of course, it can be anything.

(Effects of the Invention) As explained above, the present invention includes detecting an exception at the same time when making a condition judgment including a condition that cannot occur, and detecting an exception when the above condition judgment cannot occur. By changing this to a condition in which there is no exception, it is possible to improve the usage efficiency of the control memory and to perform exception detection with good performance.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an example of a configuration for realizing an exception detection method according to the prior art. FIG. 2 is a block diagram of an embodiment for implementing the exception detection method according to the present invention. 100... Central processing unit, 200... Control memory, 210, 220, 300, 330... Register, 230... Adder, 240, 340... Selector, 310... Logical operation circuit, 320... Data check circuit , 331-333...Flag, 3
50...Flag change circuit.

Claims (1)

[Claims] 1. In an exception detection method realized by a microprogram control method, a working register for storing data that requires exception detection and condition determination, a logic operation circuit for performing a logic operation on the data, and the logic A plurality of flag registers for displaying the result of an operation, a data check circuit for detecting an exception in the data, and a combination of the plurality of flag registers that is originally impossible when the exception is detected. and a flag selector for selecting a branch mode of a conditional branch according to the display of the plurality of flag registers, and when an exception is detected by the data check circuit, the flag change circuit An exception detection method configured to forcibly change the branch direction of the flag selector using a change circuit.