JPS61282933A - Digital signal processor - Google Patents

Abstract

PURPOSE:To access most efficiently a data sequence in a data memory by giving an address by plural registers out of general registers and using remainder registers for arithmetic of signal processing. CONSTITUTION:Data to be calculated, constants required for arithmetic, etc. are stored in data memopries X4 and Y10. The address of the data memory X4 is supplied by selecting one of 6 general registers 18. Thereafter, a constant 8 or contents of an increment register 9 are added to this address value, and the result is stored in the same register. Though the whole of registers is shared between modification of the address to the data memory X4 and arithmetic in an ALU 15, this modification is performed independently of this arithmetic in the ALU 15. A flag 19 detects zero or outputs a sign bit in accordance with the output value of an adder 7, and judgement by the adder 7 is made possible. The address of the data memory Y10 is given by an address counter 11, and contents of the address counter 11 are incremented automatically by the control.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a digital signal processing processor used in the field of digital signal processing.

BACKGROUND OF THE INVENTION Microprocessors for the purpose of digital signal processing have been developed and put into practical use. As an architectural feature, such microprocessors often have two independent data memory spaces in addition to a program storage memory in order to access data at high speed and perform high-speed calculations.

The conventional signal processing processor as described above will be described below with reference to the drawings.

FIG. 2 is a block diagram of a conventional signal processing processor. In FIG. 2, 1 is an instruction memory for storing programs, 2 is a program counter, 3 is a control unit, and 4 is a data memo! 7X, 5 and 6 are pointers PXA and PXB that give addresses to data memory X, 7 is an adder, 8
is a constant for modifying pointer PXA6 or PXBe (in this example, o, ±1.±2), 9 is an increment register for modifying pointer PXAs or PXBe, 1o is data memory Y, and 11 is a constant for modifying pointer PXA6 or PXBe. 12 is a general-purpose register (including four registers Ro, R1°R2, and R3 in this example); 13 is a multiplier; 14 is a barrel shifter; 16 is an address counter that gives an address to data memory Y;
is a circuit (ALU) that performs arithmetic operations, logical operations, and judgments.

16 is bus A and data memory X4. Data memory Y10
, Boi 7ri PXA5 , PXBe , 7)'L/Counter 11. Increment register9. general-purpose register 12,
Connected to the left input of ALU15. 17 is bus B and data memory x4. General-purpose register 12 is connected to the right input of multiplier 13 and barrel shifter 14 .

The operation of the conventional digital signal processor configured as described above will be explained.

A program is stored in the instruction memory 1, its address is given by the program counter 2, and the contents are read out to the control section 3. The control section 3 decodes this instruction and controls each section of the processor.

The data memory x4 and the data memory Y10 store data to be operated on or constants necessary for the operation. The address of data memory x4 is given by selecting either pointer PxA5 or pxBs. This value is then added to the constant 8 or the contents of the increment register 9 using the adder 7 and stored in the original pointer. In this way, pointer modification can be performed independently of operations on data sequences by ALUs. The contents of the data memory x4 accessed in this manner are read or written through the bus A16 and bus B17. Data memory Y
The ten addresses are given by address counter 11. The contents of the counter are automatically incremented by the control. The contents of the data memory Y10 accessed in this way are input to the left side of the multiplier 13 or to the bus A1e.
or written to via bus A16.

The multiplier 13 multiplies the contents of the data memory Y10 and the contents of the data memory x4 or the contents of the data memory Y10 and the contents of the general-purpose register 12 in one machine cycle, and outputs the result to the barrel shifter 14. barrel shifter 1
4 shifts either the contents of bus B17 or the contents of multiplier 13 by an arbitrary number of bits and outputs it to the right input of ALU15. The ALU 5 performs calculations and judgments using the contents of the bus A 16 and the output of the barrel shifter 14, and writes the results to one of the general-purpose registers 12.

The output of the multiplier 13 or the contents of the bus B17 converts the shift operation in the barrel shifter 14 and the operation in the ALU 15 into 1.
It is completed and written to general purpose register 12 during the machine cycle.

In such a configuration, the multiplication in the multiplier 13 and the calculation in the ALU 16 are performed in a pipeline manner, thereby performing the product-sum calculation as shown below.

Ro=Ro+(Contents of data memory Y)×(Contents of data memory At the same time, Ro is AL through bus A16.
It is input to Uls, is added to the multiplication result from one machine cycle before, and the result is accumulated in Ro in the general-purpose register 12. The data series in the data memory Y10 is accessed by the address counter 11, and sequentially by the data series pointer PXAs or PXAe in the data memory 4.

In this manner, in the signal processor, multiplication and addition of data sequences can be performed without interruption at high speed.

Problems to be Solved by the Invention However, there has been an increasing demand for accessing more data series in parallel without reducing the speed of calculations in signal processing.To do this, it is necessary to increase the number of pointers in the data memory x4. However, this leads to an increase in the chip area, and in addition, such a configuration has the problem that the registers used for the pointer and the adder 7 are used inefficiently and is not versatile.

In view of these points, the present invention provides a digital system that can access data sequences in data memory most efficiently, make maximum use of registers and adders for generating addresses, and flexibly use general-purpose registers. The purpose of the present invention is to provide a signal processing processor.

Means for Solving the Problems The present invention comprises an instruction memory for storing instructions, first and second data memories for storing data to be operated on, and a plurality of general-purpose registers for providing addresses of the first data memory. ,
an address counter giving the address of the second data memory; a first calculation unit that performs calculations and judgments using the contents of the second data memory or the general-purpose register;
The second part modifies the contents of the above general-purpose register and judges the result.
This is a digital signal processing processor equipped with an arithmetic unit.

Operation According to the present invention, with the above-described configuration, an address can be given to the first data memory using any register among the general-purpose registers, and the remaining registers can be used for signal processing operations. In this way, general-purpose registers can be allocated so as to most efficiently access the data series in the data memory. Further, the first arithmetic unit can be used not only for signal processing operations but also for address calculations, and at the same time, the second arithmetic unit can be used for operations and determinations other than address calculations.

Embodiment FIG. 1 shows a block diagram of a digital signal processing processor and sensor in an embodiment of the present invention.

In FIG. 1, 1 is an instruction memory for storing programs, 2 is a program counter, 3 is a control unit, 4 is a data memory IJ In the example R
O, R1, R2, Ra.

(including six registers R4 and Rs), 7 is an adder, 8
is a constant (0.±1.±2 in this example) used to modify the value of general-purpose register 18 using adder 7, 9 is an increment register used to modify the value of general-purpose register 18, and 1Q is data memory Y, 11 is an address counter that gives an address to data memory Y, 13 is a multiplier, 14
1 is a barrel shifter, 16 is an arithmetic/logical operation and judgment circuit (ALU), 19 is a sign flag and a zero flag for making a judgment based on the output result of the adder 7, and 2o
is data memory X4. on bus A. Data memory Y1o, address counter 11. Increment register9. General purpose register 1
s, connected to the left input of ALUls. 21 is bus B
The data memory X4° general-purpose register 189 is connected to the right input of the multiplier 13 and the barrel shifter 14.

The operation of the digital signal processing processor of this embodiment configured as described above will be explained below.0 A program is stored in the instruction memory 1, its address is given by the program counter 2, and the contents are read out to the control unit 3. . The control section 3 decodes this instruction and controls each section of the processor.

The data memory X4 and the data memory Y10 store data to be operated on or constants necessary for the operation. The address of data memory x4 is given by selecting one of the six registers of general-purpose register 18. This value is then added to the constant 8 or the contents of the increment register 9 and stored in the original register. The address modification for the data memory x4 can be performed independently of the operation in the ALU 16, although the entire register used is shared. The contents of the data memory x4 accessed in this manner are read or written through the bus A20 and the bus B21. Furthermore, the flag 19 performs zero detection and outputs a sign bit in accordance with the output value of the adder 7. This allows the adder 7 to make a determination.

The address of data memory Y10 is address counter 11
given by. The contents of address counter 11 are automatically incremented by control. The contents of the data memo 1JY10 accessed in this way are read out to the left input of the multiplier 13 and to the bus A20.
Written through 0.

Multiplier 13. Barrel shifter 14. The operation of the ALU 16 is the same as in the conventional example.

As described above, according to this embodiment, conventional data memory x
The address pointers PXAs and PXBs, which only had the function of giving 4 addresses, are incorporated into the general-purpose register 18, and the adder 7, which conventionally could only be used for modifying pointers, is made effective for the general-purpose register 18. Moreover, by providing seven lags 19 for determination, any register among the general-purpose registers 18 can be used as an address pointer for the data memory x4 according to the requirements of the algorithm used.

Further, in a routine that does not perform address modification, the adder 7 and the general-purpose register 18 can be used to perform counter operations that require judgment, etc., independently of the ALUlg operation. Thus, the adder 7 can be used effectively. Furthermore, the ALU 5 can be used not only for signal processing operations but also for address calculations if necessary.

As described in detail, according to the present invention, data in the data memory can be stored by assigning an address to the data memory using any plurality of general-purpose registers and using the remaining registers for signal processing operations. It is possible to allocate general-purpose registers so as to access the series most efficiently, and moreover, the arithmetic unit originally used to generate addresses can be efficiently used for general purposes. This allows signal processing programs to be written flexibly and to increase processing speed, which has great practical effects.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a digital signal processor according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional digital signal processor. 1...Instruction memory, 4,10...Data memory, End...Adder, 8...Constant, 9...Increment register , 13... Multiplier, 14... Barrel shifter, 16...
ALU, 1a... General purpose register, 19...
...Sine flag and zero flag.

Claims (1)

[Claims] an instruction memory that stores instructions, first and second data memories that store data to be operated on, a plurality of general-purpose registers that provide the address of the first data memory, and an address that provides the address of the second data memory. a counter; a first calculation section that performs calculations and judgments using the contents of the first and second data memories or the general-purpose registers; and a second calculation unit that modifies the contents of the general-purpose registers and judges the results. A digital signal processing processor characterized by comprising a section.