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JPS5549764A - Memory control system - Google Patents

Memory control system

Info

Publication number
JPS5549764A
JPS5549764A JP12179778A JP12179778A JPS5549764A JP S5549764 A JPS5549764 A JP S5549764A JP 12179778 A JP12179778 A JP 12179778A JP 12179778 A JP12179778 A JP 12179778A JP S5549764 A JPS5549764 A JP S5549764A
Authority
JP
Japan
Prior art keywords
register
registers
memory unit
contents
memory system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12179778A
Other languages
Japanese (ja)
Inventor
Haruo Kohama
Masao Togawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP12179778A priority Critical patent/JPS5549764A/en
Publication of JPS5549764A publication Critical patent/JPS5549764A/en
Pending legal-status Critical Current

Links

Landscapes

  • Debugging And Monitoring (AREA)
  • Memory System (AREA)

Abstract

PURPOSE: To make it possible to substitute temporarily certain contents of a memory unit by another contents without destruction of contents of the memory unit in a simple operation.
CONSTITUTION: In the memory system consisting of memory unit 3, access address register 1, write data register 2 and read data register 4, a register stack part consisting of register stack 8 constituted by plural registers 801W805 and indication elements 701W705 indicating whether registers are available or not, control circuit 7 and address agreement detection circuit 6 which compares address information of access address register 1 with address information of registers 801W805, gate circuits 101W105, and indication element 5 which indicates whether register stack 8 is available or not to switch the operation with only the normal memory system and the operation with a constitution including the normal memory system and the register stack above the added.
COPYRIGHT: (C)1980,JPO&Japio
JP12179778A 1978-10-03 1978-10-03 Memory control system Pending JPS5549764A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12179778A JPS5549764A (en) 1978-10-03 1978-10-03 Memory control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12179778A JPS5549764A (en) 1978-10-03 1978-10-03 Memory control system

Publications (1)

Publication Number Publication Date
JPS5549764A true JPS5549764A (en) 1980-04-10

Family

ID=14820145

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12179778A Pending JPS5549764A (en) 1978-10-03 1978-10-03 Memory control system

Country Status (1)

Country Link
JP (1) JPS5549764A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01177139A (en) * 1988-01-05 1989-07-13 Nec Corp Instruction substituting system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01177139A (en) * 1988-01-05 1989-07-13 Nec Corp Instruction substituting system

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