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JPS5627451A - Data processor - Google Patents

Data processor

Info

Publication number
JPS5627451A
JPS5627451A JP10125979A JP10125979A JPS5627451A JP S5627451 A JPS5627451 A JP S5627451A JP 10125979 A JP10125979 A JP 10125979A JP 10125979 A JP10125979 A JP 10125979A JP S5627451 A JPS5627451 A JP S5627451A
Authority
JP
Japan
Prior art keywords
address
μpg
logging
register
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10125979A
Other languages
Japanese (ja)
Inventor
Masahiko Kida
Hitotsugu Ukon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP10125979A priority Critical patent/JPS5627451A/en
Publication of JPS5627451A publication Critical patent/JPS5627451A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make logging possible without any address stop by providing a circuit that causes an interruption when the contents of logging address register LAR agree with the address of microprogram μPG in process of execution.
CONSTITUTION: Through the panel, address A of μPG where logging to be carried out is previously set in LAR8 and when the contents of address register AR2 agree with those of LAR8, comparing circuit 9 sends an identity signal to set FF10 while interruption control circuit 11 sends a signal to address control circuit 1. Circuit 1 transfers contents A+1 of AR2 to address stand-by register 7 and sets the start address of new μPG in AR2. The new μPG stores information on the internal register and others in the logging area of control storage 3, read address B of μPG, at which the next logging is to be executed, out of memory unit 12, and sets and reset LAR8 and FF10 respectively. Next, address A+1 is returned from register 7 to AR2 and the original μPG is executed.
COPYRIGHT: (C)1981,JPO&Japio
JP10125979A 1979-08-10 1979-08-10 Data processor Pending JPS5627451A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10125979A JPS5627451A (en) 1979-08-10 1979-08-10 Data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10125979A JPS5627451A (en) 1979-08-10 1979-08-10 Data processor

Publications (1)

Publication Number Publication Date
JPS5627451A true JPS5627451A (en) 1981-03-17

Family

ID=14295909

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10125979A Pending JPS5627451A (en) 1979-08-10 1979-08-10 Data processor

Country Status (1)

Country Link
JP (1) JPS5627451A (en)

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