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JPS5595152A - Microinstruction execution control system - Google Patents

Microinstruction execution control system

Info

Publication number
JPS5595152A
JPS5595152A JP136179A JP136179A JPS5595152A JP S5595152 A JPS5595152 A JP S5595152A JP 136179 A JP136179 A JP 136179A JP 136179 A JP136179 A JP 136179A JP S5595152 A JPS5595152 A JP S5595152A
Authority
JP
Japan
Prior art keywords
error
bit
ecc4
instruction
ecc
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP136179A
Other languages
Japanese (ja)
Inventor
Hironari Okuda
Yoshihiko Kadowaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP136179A priority Critical patent/JPS5595152A/en
Publication of JPS5595152A publication Critical patent/JPS5595152A/en
Pending legal-status Critical Current

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  • Detection And Correction Of Errors (AREA)

Abstract

PURPOSE: To improve the effect of ECC without deteriorating the performance of a system, by executing microinstructions by using codes obtained by correcting only words having an error in the past by an error detecting correction circuit.
CONSTITUTION: An instruction read out from control memory CS1 consists of a microinstruction word group, humming code and E bit 3 for ECC control. The read instruction is inputted to ECC circuit 4 and when an error is detected, ECC4 sends an error detection signal to microinstruction execution part EC7, so that an instruction in execution will be interrupted immediately. Then, ECC4 sets E bit 3 to "1" and E-bit write address register ECSAR8 writes it to CS1. When E bit 3 read out from CS1 is "1", an error correction is made by the humming code and then the output of ECC4 is set to control memory data register CSDR6 to send an instruction execution indication signal to EC7. At this time, when no error is detected by ECC4, the E bit is set to "0" and written to CS1.
COPYRIGHT: (C)1980,JPO&Japio
JP136179A 1979-01-12 1979-01-12 Microinstruction execution control system Pending JPS5595152A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP136179A JPS5595152A (en) 1979-01-12 1979-01-12 Microinstruction execution control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP136179A JPS5595152A (en) 1979-01-12 1979-01-12 Microinstruction execution control system

Publications (1)

Publication Number Publication Date
JPS5595152A true JPS5595152A (en) 1980-07-19

Family

ID=11499345

Family Applications (1)

Application Number Title Priority Date Filing Date
JP136179A Pending JPS5595152A (en) 1979-01-12 1979-01-12 Microinstruction execution control system

Country Status (1)

Country Link
JP (1) JPS5595152A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5958547A (en) * 1982-09-28 1984-04-04 Fujitsu Ltd Error processing system of microprogram controller

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5958547A (en) * 1982-09-28 1984-04-04 Fujitsu Ltd Error processing system of microprogram controller
JPH044616B2 (en) * 1982-09-28 1992-01-28

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