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JPS5552598A - Data processor - Google Patents

Data processor

Info

Publication number
JPS5552598A
JPS5552598A JP12414378A JP12414378A JPS5552598A JP S5552598 A JPS5552598 A JP S5552598A JP 12414378 A JP12414378 A JP 12414378A JP 12414378 A JP12414378 A JP 12414378A JP S5552598 A JPS5552598 A JP S5552598A
Authority
JP
Japan
Prior art keywords
address
error
signal
main memory
buffer area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12414378A
Other languages
Japanese (ja)
Inventor
Makoto Muramatsu
Seiichiro Yamamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP12414378A priority Critical patent/JPS5552598A/en
Publication of JPS5552598A publication Critical patent/JPS5552598A/en
Pending legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • Retry When Errors Occur (AREA)

Abstract

PURPOSE: To continue a data process by eliminating an influence of an unrecoverable error generated in the buffer area of a main memory unit on an initial program, by providing a method of reporting an address of the main memory where the unrecoverable error is generated.
CONSTITUTION: Access to the buffer area of the main memory is attained by main memory address signal 1 and read data 8 is inputted to an error detection circuit, where error detection is performed. Unrecoverable error signal 9 is switched ON and error recoverable error signal 10 is ON to indicate corrections of data 8. Then, comparator circuit 3 makes a comparison between the initial address of a previously- recognized buffer area and main memory address signal 1; when the address resides in the buffer area, program storage area signal 5 is On and when not, buffer area signal 4 is ON. Next, the address of unrecoverable error 9 is temporarily stored in error address register 12 and at every time when unrecoverable error 9 is generated, address signal 1 is latched to continue a data process.
COPYRIGHT: (C)1980,JPO&Japio
JP12414378A 1978-10-11 1978-10-11 Data processor Pending JPS5552598A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12414378A JPS5552598A (en) 1978-10-11 1978-10-11 Data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12414378A JPS5552598A (en) 1978-10-11 1978-10-11 Data processor

Publications (1)

Publication Number Publication Date
JPS5552598A true JPS5552598A (en) 1980-04-17

Family

ID=14877982

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12414378A Pending JPS5552598A (en) 1978-10-11 1978-10-11 Data processor

Country Status (1)

Country Link
JP (1) JPS5552598A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60132250A (en) * 1983-12-21 1985-07-15 Yamatake Honeywell Co Ltd Restarting method of control device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60132250A (en) * 1983-12-21 1985-07-15 Yamatake Honeywell Co Ltd Restarting method of control device

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