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JPS5580900A - Memory device - Google Patents

Memory device

Info

Publication number
JPS5580900A
JPS5580900A JP15424378A JP15424378A JPS5580900A JP S5580900 A JPS5580900 A JP S5580900A JP 15424378 A JP15424378 A JP 15424378A JP 15424378 A JP15424378 A JP 15424378A JP S5580900 A JPS5580900 A JP S5580900A
Authority
JP
Japan
Prior art keywords
output
register
circuit
result
report
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15424378A
Other languages
Japanese (ja)
Inventor
Itaru Ishikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP15424378A priority Critical patent/JPS5580900A/en
Publication of JPS5580900A publication Critical patent/JPS5580900A/en
Pending legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE: To prevent the disturbance of the process sequence caused by the same factor and thus to enhance the maintenance properties by giving a comparison between the address information given from the processor and the contents of the address memory part and then suppressing the report at the correction success reading time.
CONSTITUTION: The address information is sent to the memory device via interface signal 50 to the processor and then set to register 100 to be held, and the output 101 is given an access to normal memory module 300 through decoder 200. And the reading information is set to reading information register 500 through correction circuit 400. The result of the check obtained at circuit 400 is set to result storage register 600. On the other hand, output 103 of circuit 100 and number memory part 700 are searched successively, and the result receives comparison 10. And when coincidence output 11 is obtained, output 601 of register 600 is made ineffective 303 to give suppression to the report of the correction success.
COPYRIGHT: (C)1980,JPO&Japio
JP15424378A 1978-12-15 1978-12-15 Memory device Pending JPS5580900A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15424378A JPS5580900A (en) 1978-12-15 1978-12-15 Memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15424378A JPS5580900A (en) 1978-12-15 1978-12-15 Memory device

Publications (1)

Publication Number Publication Date
JPS5580900A true JPS5580900A (en) 1980-06-18

Family

ID=15579956

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15424378A Pending JPS5580900A (en) 1978-12-15 1978-12-15 Memory device

Country Status (1)

Country Link
JP (1) JPS5580900A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5848297A (en) * 1981-09-14 1983-03-22 Nec Corp Processing system for 1-bit error fault of storage device
US10813617B2 (en) 2015-06-22 2020-10-27 Fujifilm Corporation Radiation emitting device, method for controlling radiation emitting device, and program

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5848297A (en) * 1981-09-14 1983-03-22 Nec Corp Processing system for 1-bit error fault of storage device
US10813617B2 (en) 2015-06-22 2020-10-27 Fujifilm Corporation Radiation emitting device, method for controlling radiation emitting device, and program

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