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JPS5548900A - Cash memory - Google Patents

Cash memory

Info

Publication number
JPS5548900A
JPS5548900A JP12089078A JP12089078A JPS5548900A JP S5548900 A JPS5548900 A JP S5548900A JP 12089078 A JP12089078 A JP 12089078A JP 12089078 A JP12089078 A JP 12089078A JP S5548900 A JPS5548900 A JP S5548900A
Authority
JP
Japan
Prior art keywords
error
data
detected
error correction
correction code
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12089078A
Other languages
Japanese (ja)
Inventor
Wataru Shimoda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP12089078A priority Critical patent/JPS5548900A/en
Publication of JPS5548900A publication Critical patent/JPS5548900A/en
Pending legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To reduce the hardware and to increase the reliability of data at memory section, by performing error correction through the production of error correction code based on the information from the main memory unit.
CONSTITUTION: The error correction code is generated 5 based on the data 2 and address 1 given from the main memory unit, and this developed code and the data 2 are stored 3 at a given location. Further, the data error is detected based on the stored data, error correction code and address 2. At this detection, if any address error is present, the address is not corrected and if data and error correction code are detected for error, the data error is corrected 6. Further, if no error is detected or the error correction code is detected for error, data is outputted. Further, correction disable error is detected, then the same information is read out from the main memory unit. As a result, the amount of hardware can be reduced.
COPYRIGHT: (C)1980,JPO&Japio
JP12089078A 1978-09-29 1978-09-29 Cash memory Pending JPS5548900A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12089078A JPS5548900A (en) 1978-09-29 1978-09-29 Cash memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12089078A JPS5548900A (en) 1978-09-29 1978-09-29 Cash memory

Publications (1)

Publication Number Publication Date
JPS5548900A true JPS5548900A (en) 1980-04-08

Family

ID=14797507

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12089078A Pending JPS5548900A (en) 1978-09-29 1978-09-29 Cash memory

Country Status (1)

Country Link
JP (1) JPS5548900A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5847555A (en) * 1981-09-17 1983-03-19 Toshiba Corp Producing device for die cast parts

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5847555A (en) * 1981-09-17 1983-03-19 Toshiba Corp Producing device for die cast parts
JPH0346222B2 (en) * 1981-09-17 1991-07-15 Tokyo Shibaura Electric Co

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