JPS5789148A - Method for controlling interruption - Google Patents
Method for controlling interruptionInfo
- Publication number
- JPS5789148A JPS5789148A JP16616180A JP16616180A JPS5789148A JP S5789148 A JPS5789148 A JP S5789148A JP 16616180 A JP16616180 A JP 16616180A JP 16616180 A JP16616180 A JP 16616180A JP S5789148 A JPS5789148 A JP S5789148A
- Authority
- JP
- Japan
- Prior art keywords
- error
- circuit
- signal
- control section
- corrected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2215—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test error correction or detection circuits
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
Abstract
PURPOSE:To secure prior processings and to improve processing efficiencies, by installing a means which deters an interruption until execution of a highly prior processing is completed, when the interruption is issued during the course of execution of the high priority processing by a processor. CONSTITUTION:Before the function of an error correction controlling circuit 4 is tested, a control section 6 issues a signal and sets a signal ''1'' to an inhibit bit column (e) of a register 7. Because of this, a set signal S is issued from a processor 5 and a flip flop 10 is set. Therefore, an AND circuit 9 is closed and interrupt signals B1-B3 are deterred. The control section 6 writes error data A which intentionally generate an error in a memory 1 through a writing circuit 3. Error data read out from a reading circuit 2 are corrected by the error correction controlling circuit 4. This corrected output signal C is checked by the control section 6, and when it is correctly corrected, it is confirmed that the error correcting function is under a normal condition.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16616180A JPS5789148A (en) | 1980-11-26 | 1980-11-26 | Method for controlling interruption |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16616180A JPS5789148A (en) | 1980-11-26 | 1980-11-26 | Method for controlling interruption |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5789148A true JPS5789148A (en) | 1982-06-03 |
Family
ID=15826195
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16616180A Pending JPS5789148A (en) | 1980-11-26 | 1980-11-26 | Method for controlling interruption |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5789148A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60108935A (en) * | 1983-11-18 | 1985-06-14 | Oki Electric Ind Co Ltd | Interruption processing system of microcomputer |
| JPS6228837A (en) * | 1985-07-31 | 1987-02-06 | Toshiba Corp | Interruption signal control system |
-
1980
- 1980-11-26 JP JP16616180A patent/JPS5789148A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60108935A (en) * | 1983-11-18 | 1985-06-14 | Oki Electric Ind Co Ltd | Interruption processing system of microcomputer |
| JPH0330172B2 (en) * | 1983-11-18 | 1991-04-26 | ||
| JPS6228837A (en) * | 1985-07-31 | 1987-02-06 | Toshiba Corp | Interruption signal control system |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS5622143A (en) | Error processing system | |
| JPS5758210A (en) | Error correction range controlling circuit | |
| JPS5797151A (en) | Instruction storage device | |
| JPS5789148A (en) | Method for controlling interruption | |
| JPS5792411A (en) | Pcm signal processor | |
| JPS55157042A (en) | Information processor | |
| JPS5318925A (en) | Memory control unit | |
| JPS57130150A (en) | Register control system | |
| JPS563496A (en) | Memory control circuit | |
| JPS55120252A (en) | Error control system | |
| JPS5622291A (en) | Bit error correction method for memory | |
| JPS573151A (en) | Test system for 1-chip microcomputer | |
| JPS5595152A (en) | Microinstruction execution control system | |
| KR840000977B1 (en) | Floppy disc I / O device | |
| JPS5363829A (en) | Generation control system of interrupt signal and interrupt circuit its execution | |
| JPS5542343A (en) | Control system for memory unit | |
| JPS5631143A (en) | Preventing system for program runaway | |
| JPS5668997A (en) | Error correction system | |
| JPS58175200A (en) | Checking system of storage system | |
| JPS5569858A (en) | Error detection and correction system | |
| JPS54104751A (en) | Data processor | |
| JPS5688550A (en) | Pseudo error transmission system | |
| JPS54129948A (en) | Data processor | |
| JPS55146553A (en) | Controlling circuit of program of microcomputer | |
| JPS5638636A (en) | Data processing unit |