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JPS5718098A - Retrial system for memory write-in - Google Patents

Retrial system for memory write-in

Info

Publication number
JPS5718098A
JPS5718098A JP9310580A JP9310580A JPS5718098A JP S5718098 A JPS5718098 A JP S5718098A JP 9310580 A JP9310580 A JP 9310580A JP 9310580 A JP9310580 A JP 9310580A JP S5718098 A JPS5718098 A JP S5718098A
Authority
JP
Japan
Prior art keywords
write
data
control section
error
detected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9310580A
Other languages
Japanese (ja)
Other versions
JPS6041380B2 (en
Inventor
Katsunobu Noda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55093105A priority Critical patent/JPS6041380B2/en
Publication of JPS5718098A publication Critical patent/JPS5718098A/en
Publication of JPS6041380B2 publication Critical patent/JPS6041380B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Retry When Errors Occur (AREA)

Abstract

PURPOSE:To increase the processing efficiency of a CPU, by storing address information and write-in data at a storage control section and making retrial of memory write-in at a storage control section, when an error is detected from the storage device. CONSTITUTION:When a write-in request of 0 side CPU is received, address information, write-in data, and byte mark information are stored in registers 5-6, 6-0, 7-0 of a storage control section 2. In case of full-write, the address information and the write-start signal of a write-in data register 5-0 adding the data of the register 6-0 with the error correction code are transmitted to a memory device 1, where it is written in a memory array 12. When an error is detected in the device 1 and a correctable error is detected at the control section 2 with partial-write, a control circuit 4 uses stored information and data for re-write processing.
JP55093105A 1980-07-07 1980-07-07 Memory write retry method Expired JPS6041380B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55093105A JPS6041380B2 (en) 1980-07-07 1980-07-07 Memory write retry method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55093105A JPS6041380B2 (en) 1980-07-07 1980-07-07 Memory write retry method

Publications (2)

Publication Number Publication Date
JPS5718098A true JPS5718098A (en) 1982-01-29
JPS6041380B2 JPS6041380B2 (en) 1985-09-17

Family

ID=14073238

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55093105A Expired JPS6041380B2 (en) 1980-07-07 1980-07-07 Memory write retry method

Country Status (1)

Country Link
JP (1) JPS6041380B2 (en)

Also Published As

Publication number Publication date
JPS6041380B2 (en) 1985-09-17

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