JPH07263767A - Planer type high-temperature superconducting integrated circuit using ion implantation - Google Patents

Abstract

PURPOSE: To manufacture a planar type high-temperature superconducting integrated circuit by using ion implantation by providing a substrate, a first HTS layer, a second HTS, i.e., dielectric/contact layer and a third HTS layer. CONSTITUTION: A first HTS layer 58 may be, for example, first adhered and patterned by using photolithography. Regions 62, 64 of the layer 58 are exposed by using ion implantation, superconducting characteristic of the regions 62, 64 are altered, while non-alternating HTS region 60 retains the superconducting characteristics. A second HTS layer 68 can be adhered and patterned by using photolithography. Regions 70, 71 are exposed by using ion implantation, superconducting characteristic of the regions 70, 71 are altered, while a non- altering region 69 retains the superconducting characteristic. Then, a third HTS layer 72 is adhered and patterned on a dielectic/contact layer 68, thereby completing an HTS integrated circuit 50.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high temperature superconducting integrated circuit, and more particularly to a planar type high temperature superconducting integrated circuit manufactured by using ion implantation.

[0002]

BACKGROUND OF THE INVENTION High temperature superconducting (HTS) integrated circuits typically include a first HTS layer patterned and deposited on a substrate using photolithography. First HT
Unwanted portions of the S layer are physically etched away using various techniques such as ion milling, reactive ion etching, plasma etching and wet etching. An insulating dielectric layer is formed on the HTS layer. The second HTS layer is then patterned and deposited. Further dielectric layers and HTS layers can be alternately formed on top of this second HTS layer.

In order to effectively grow the second HTS layer, the underlying dielectric layer must be monocrystalline or highly oriented (as opposed to polycrystalline or amorphous).
However, growing an epitaxial dielectric layer over the patterned first HTS layer is very difficult. Because a lattice match is required between the dielectric layer and the two distinct different surfaces, between the substrate layer and the two distinct different surfaces, and between the substrate and the first HTS layer. This is because that. In addition to giving this lattice match,
Proper crystal growth must be maintained by the angled portion formed at the edge of the first HTS layer.

The stress, thickness, uniformity and compatibility of the dielectric layer must also be considered. A short circuit may occur between the first and second HTS layers near the edge of the first layer through the dielectric layer. Further, the second HTS layer is deposited over the non-planar dielectric layer (mainly the second HTS layer is the first HTS layer).
The second HTS layer (as it intersects the TS layer) may experience breaks, line discontinuities, and / or encounter a significant reduction in supercurrent carrying capability (Jc). is there. This is due to disruption of the crystallographic orientation near the edges of the first layer and / or non-uniform crystal thickness (eg, the crystal is too thin). The above problems increase as additional dielectric and HTS layers are formed.

[0005]

Therefore, a high temperature superconducting integrated circuit that addresses the above problems is desired.

First HTS layer, dielectric layer and second HT
When the S layer is deposited in discrete steps, contacts can be formed between the first and second HTS layers through the contact holes in the dielectric layer. Prior to patterning and depositing the second HTS layer, the top interface of the first HTS layer is typically cleaned using chemical etching or ion cleaning. Such cleaning may cause damage or change in the upper interface of the first HTS layer and form a thin non-superconducting layer to cause low supercurrent carrying capability (Jc) or non-superconductivity. There is.

[0007]

A multilayer planar high temperature superconducting integrated circuit formed on a substrate comprises a first planar high temperature superconducting (HTS) layer deposited and patterned on the substrate. The layer has a central region and abuts the central region 2
And two facing areas. Ion implantation is used to destroy the superconductivity of these opposing regions without interrupting the lattice structure of these opposing regions. First
A second flat HTS layer is deposited and patterned on the HTS layer of, and the second layer includes a central region and two opposing regions abutting the central region. Ion implantation is used to destroy the superconductivity of these opposing regions without interrupting the lattice structure of these opposing regions. A third flat HTS layer is deposited and patterned on top of the second HTS layer.

In accordance with another embodiment of the present invention, a multi-layer planar high temperature superconducting integrated circuit is formed on a substrate, the integrated circuit having a first planar high temperature deposited and patterned on the substrate. A superconducting (HTS) layer is provided, the layer including a central region and two opposing regions abutting the central region. Ion implantation at the first implant energy level is used to destroy superconductivity in the facing regions without blocking lattice-structured ions in the facing regions. Using ion implantation at a second energy level lower than the first implant energy level, superconductivity in the upper part of the central region is destroyed and contacts are formed without breaking the lattice structure in the upper part of the central region. . A second HTS layer is deposited and patterned on top of the first HTS layer, the second layer abutting opposing regions, contacts and top of the first layer.

In accordance with yet another embodiment of the present invention, a planar high temperature superconducting integrated circuit is formed on a substrate, the integrated circuit having a first high temperature superconducting deposited and patterned on the substrate. (HTS) layer. The HTS layer comprises a lower portion having an opposing region that abuts the central region.
The facing region is bombarded using ion implantation with high energy deep range ions, destroying the superconductivity of the lower facing region. The middle portion has an opposing region that abuts the central region. These opposing regions are bombarded using ion implantation with ions in the intermediate range of intermediate energies, destroying the superconductivity of the opposing regions of the intermediate region. The upper part comprises the central superconducting region.

Other objects, features and advantages of the present invention will be readily apparent. Various effects of the present invention will be readily apparent to those skilled in the art from the following detailed description with reference to the accompanying drawings.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to FIG. 1, a high temperature superconducting (HTS) integrated circuit 10 of the prior art is first deposited and patterned on a substrate 19 using, for example, photolithography.
HTS layer 18 of The HTS layer is composed of yttrium-barium-copper-oxygen (Y-Ba-Cu-O),
Bismuth-strontium-calcium-copper-oxygen (B
i-Sr-Ca-Cu-O), and thallium-barium-calcium-copper-oxygen (T1-Ba-Ca-Cu-).
O). Other materials will be readily apparent.

Undesired portions of HTS layer 18 are physically etched using various techniques, such as ion milling, reactive ion etching, plasma etching and wet etching. It will be apparent that other etching and lift-off techniques can also be used. First HT
An insulating dielectric layer 22 is deposited and patterned on the S layer 18. This dielectric layer 22 is made of SrTiO ₃ and L
It can be formed using aAlO ₃ . Other materials will be readily apparent. Then, a second layer is formed on the dielectric layer 22.
HTS layer 26 is deposited and patterned. As is apparent from FIG. 1, the second HTS layer 26 is
The first HTS layer 18 is contacted along the top surface of the layer 18.
If desired, use the second HTS layer 2 as described above.
Further dielectric layers and HTS layers can be alternately formed on 6.

In order for the second HTS layer 26 to grow efficiently, the underlying dielectric layer 22 must be epitaxial, in other words single crystal or highly oriented (polycrystalline). Or in contrast to amorphous). However, it is very difficult to grow the epitaxial dielectric layer 22 on the first HTS layer 18. This is because a lattice match is required between the dielectric layer 22 and the two separate and distinct surfaces, namely the substrate 19 and the first HTS layer 18. In addition to providing this lattice match, the edge 30 of the first HTS layer 18
And 32 must maintain the proper crystallinity length.

Further, the stress, thickness, uniformity of the dielectric layer 22,
And compatibility must also be considered. A short circuit occurs between the first HTS layer 18 and the second HTS layer 26 through the dielectric layer 22 near the edges 30 and 32 of the first layer 18, degrading the performance of the HTS integrated circuit 10. Sometimes.
In addition, the second HTS layer 26 is a non-planar dielectric layer 22.
Deposited and patterned on (primarily the second HT
Since the S-layer 26 intersects the first HTS layer 18), the second HTS layer 26 may cause breaks, line discontinuities, and / or supercurrent carrying capability (Jc). You may encounter a significant drop. This is due to disruption of crystal orientation and / or non-uniform crystal thickness (thin crystals become thin). The above problems increase as additional dielectric and HTS layers are formed.

When the first HTS layer 18, the dielectric layer 22 and the second HTS layer 26 are deposited and patterned in separate steps, the first and second via the contact holes of the dielectric layer 22. A contact is formed between the HTS layers 18 and 26. The upper interface of the first HTS layer 18 is typically the second interface.
Before the HTS layer 26 is deposited and patterned, it is cleaned using chemical etching or ion cleaning. Such cleaning can cause damage and changes at the upper interface of the first HTS layer and can form a thin non-superconducting layer. The thin non-superconducting layer results in non-superconducting contacts or superconducting contacts with low supercurrent carrying capability (Jc).

Referring to FIG. 2, the first H according to the present invention.
The TS integrated circuit 50 includes a substrate 54, a first HTS layer 58 including an unmodified HTS region 60 and modified HTS regions 62, 64, an unmodified HTS region 69 and modified HTS regions 70, 71. A second HTS or dielectric / contact layer 68 including a third HTS layer 72.
The first HTS layer 58 can be first deposited and patterned using, for example, the photolithographic techniques described above. Other techniques are readily apparent. The regions 62 and 64 of the first HTS layer 58 are exposed using ion implantation and the superconducting properties of the regions 62 and 64 are modified to form modified HTS regions 62 and 64, while unmodified. The HTS region 60 retains superconducting properties.

The second HTS layer 68 can also be deposited and patterned using photolithographic techniques. Regions 70 and 71 are exposed to ion implantation to alter the superconducting properties of regions 70 and 71,
The unaltered region 69 retains superconducting properties. The unaltered area 69 acts as a contact and the altered areas 70 and 7
2 acts as a dielectric.

A third HTS layer 72 is then deposited and patterned on the planar dielectric / contact layer 68 to complete the first HTS integrated circuit 50. If additional layers are desired, additional dielectric and HTS layers can be deposited and patterned over the planar dielectric layer 68. Also, if desired, similar to the first HTS layer 58 described above, ion implantation is used in the third HTS layer 72 to form modified regions 75, 76 and unmodified region 78. be able to. Third HTS layer 7
Rather than implanting two, regions 75 and 76 can be removed if desired using a wet or dry etching step (eg, reactive ion etching, ion milling, etc.).

As will be appreciated, a photoresist / mask can be used to demarcate the modified and unmodified regions during ion implantation. Other techniques can also be used. Deposit and pattern a planar dielectric / contact layer 68 on the planar HTS layer 58, or a third HT
Prior to depositing and patterning the S layer 72, the first HTS
An anneal step is performed on the layer 58 and / or the second HTS (or dielectric / contact) layer 68 to anneal out ion implant damage and to chemically modify the implant species and oxygen in the modified HTS region. Activated bonds and modified H implanted implants
Out-spreading from the TS domain to the unchanged HTS domain can be minimized.

The first HTS integrated circuit 50 modifies the superconducting properties of the flat HTS region using ion implantation techniques rather than physically removing the regions using etching or lift-off techniques. Is. The result is a flat surface for subsequent layers. Ion implant species are selected to modify the chemical and electrical properties of the area to be modified without breaking the lattice structure. Such ion implantation without destroying the lattice structure is disclosed in US Pat. No. 5,194,419 to Shiga et al., Which is hereby incorporated by reference.

For example, the implant species can be selected to form a stable chemical bond with oxygen atoms in the copper-oxide plane of the HTS perovskite, which results in non-conducting properties of the implanted region. The number of oxygen atoms available in the perovskite unit cell for conversion to superconductivity can be reduced. Converting the modified region to non-superconducting using ion implantation that damages the crystal lattice is unacceptable. This is because the crystal lattice structure of the modified region must be maintained so that additional HTS layers can be deposited and patterned thereon.

A second HTS integrated circuit 100 according to the present invention is shown in FIG. The first HTS layer 104 is deposited and patterned on the substrate 108 using photolithography. Using the first mask, the first HTS layer 1
The 04 first and second regions 112 and 114 are exposed to ion implantation (using the first implant energy) to neutralize their superconducting properties. Modified portion using a second mask to implant the top of region 116 with a second implant energy that is lower than the first implant energy used for modified HTS regions 112 and 114. 1
18, 120 and contacts 121 are defined. Ion is
Since it is implanted with the second low implant energy, the ions penetrate only the portion of the thickness "D" of the HTS layer 104. The modified portions 118 and 120 are
It is converted to a dielectric or high resistance non-superconducting layer. A second HTS layer 122 is deposited and patterned on the flat first layer 104. Annealing can be performed before forming the second HTS layer 122.

The modified regions 124 and 126 and the unmodified region 128 can be formed in the second HTS layer 122 as previously described in connection with the HTS layer 72 of FIG. Alternatively, using wet or dry etching, H 2
The regions 124 and 126 of the TS layer 122 can also be removed. First and second HTS integrated circuits 50 and 100
The implant species used for must have a low diffusion length in the material selected for the HTS layer. This is because a temperature cycle of 600 to 800 ° C. occurs during the subsequent formation of the dielectric and / or HTS layer. As can be seen, the planar HTS integrated circuits 50 and 100 show short circuits, line discontinuities, disconnections,
And the risk of reduction of superconducting transport capacity (Jc)
Reduced more than TS integrated circuit.

Referring to FIG. 4, a third H according to the present invention is used.
The TS integrated circuit 250 comprises a single HTS film, layer 251 patterned and deposited on a substrate 252. In a first implantation step with a first photoresist / mask, high energy deep range ions are implanted in regions 253 and 254 and adjacent to substrate 252, HTS film or layer 25.
1 at the bottom 258 of the first HTS region 256 of thickness "A"
Is contoured. Regions 253 and 254 are converted to relatively high resistance non-superconducting regions or dielectrics during ion implantation.

Second using a second photoresist / mask
During the implantation step of, a medium range of intermediate energy ions are implanted to form non-superconducting dielectric regions 260 and 262 in a single HTS film or layer 251 at an intermediate portion 264 (having a thickness "B"). Form. The contact region 268 remains unchanged (superconducting) due to the intermediate range (ie, second) ion implantation stage of intermediate energies.

Third Using Third Photoresist / Mask
Low energy, low range ions are implanted in the upper portion 272 (having a thickness "C") during the implantation step of the dielectric, or high resistance non-superconducting region 274.
And 276 are formed and a second unmodified HTS region 280 is formed.
Is defined. Alternatively, instead of the third implantation step, wet or dry etching steps (eg, reactive ion etching, ion milling, etc.) may be used to remove regions 274 and 276 if desired.

As is apparent from FIG. 4, the first HTS region 256 is generally wider than the contact region 268. Therefore, the deep range of ions used in the first implantation stage to modify the regions 253 and 254 will not damage the contact region 268. Area 2
High energy deep range ions implanted in 53 and 254 cause some damage to regions 260 and 262 of middle portion 264. Similarly, the high energy deep range ions and the medium energy mid range ions cause the second HTS region 280 and the region 27 to move.
4,276 suffers some physical damage. However, the first HTS region 256 and contacts 268 remain "pure". If desired, an anneal operation can be used to restore the superconducting properties of the second HTS region 280.

FIG. 5 shows the ion densities 300, 302 and 304, respectively, of the first, second and third implantation steps as a function of penetration depth. As will be appreciated, the implanted ions preferably have a low scatter or distribution (σ). A, B and C correspond to the thickness of the lower, middle and upper portions 258, 264 and 272.

The species of ions used to implant during the ion implantation steps 1 to 3 are physical to the top of the HTS film or layer 251, especially at the location where the second HTS region 280 is to be delineated. Must be chosen to minimize the amount of damage done. To minimize the physical damage, the second HTS area 2
Reduce or eliminate the anneal process required to restore the 80's superconducting properties.

Multi-layer and single-layer planar H according to the invention
It will be appreciated that TS integrated circuits reduce the risk of short circuits, line discontinuities, disconnections, and reduced superconducting carrier capability (Jc) over conventional HTS integrated circuits. Furthermore, FIG.
Implanting a single HTS layer 251 as described above in relation to the HTS integrated circuit 10 according to the prior art.
Eliminates problems associated with chemical etching and / or ionic cleaning of the upper interface between the dielectric layer 22 and the first HTS layer 18.

HTS integrated circuit 250 simplifies the manufacture of HTS integrated circuits. Only the thick layer of HTS film 251 is deposited and patterned first. In this way, problems of crystal lattice mismatch and crystal growth orientation / interface can be avoided. The contact 268 is superconducting and is the exact HT of the first and second HTS regions 256 and 280.
It has S film characteristics. The contact point 268 is a “pure region” that does not have an artificially formed interface. Thus, the contacts 268 are superconducting and can carry high superconducting current densities.

Single HTS Layer 2 of HTS Integrated Circuit 250
The second HTS region 280 has substantially the same properties as the first HTS layer 256 because 51 can be deposited and patterned in one step. Instead of using the thin film deposition technique, the intermediate portion 264 is uniformly implanted to provide contact areas 268 and modified areas 260 and 26.
By forming 2 and 2, the intermediate portion 264 (or dielectric and contact) is less susceptible to growth related problems such as pinholes and cracks, which are defects in the dielectric film. Thus, the HTS integrated circuit according to the present invention provides a simple manufacturing method, low defect rate, low cost, and excellent device performance and characteristics.

From the above description and claims, various effects of the present invention will be apparent to those skilled in the art.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a high temperature superconducting (HTS) integrated circuit according to the prior art in which a first HTS layer contacts a second HTS layer in the contact area formed by a dielectric layer.

FIG. 2 is a cross-sectional view of a first multilayer planar HTS integrated circuit according to the present invention.

FIG. 3 is a cross-sectional view of a second multilayer planar HTS integrated circuit according to the present invention.

FIG. 4 is a cross-sectional view of a high temperature semiconductor integrated circuit according to the present invention formed from a single HTS layer.

5 is a diagram showing ion energy of ions used for manufacturing the HTS integrated circuit of FIG. 4;

[Explanation of symbols]

 50 first HTS integrated circuit 54 substrate 58 first HTS layer 60 unmodified HTS region 62, 64 modified HTS region 68 second HTS layer 69 unmodified HTS region 70, 71 modified HTS region 72 Third HTS layer 100 Second HTS integrated circuit 250 Third HTS integrated circuit

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] March 13, 1995

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Claims

[Correction method] Change

[Correction content]

[Claims]

 ─────────────────────────────────────────────────── ——————————————————————————————————————————————————————————————————————————————————————————————————————————————— are you using this item?

Claims (31)

[Claims] 1. A multi-layer planar high temperature superconducting integrated circuit formed on a substrate, comprising: a central region deposited and patterned on the substrate, and two opposing regions abutting the central region. A flat high temperature superconducting (HTS) layer, wherein ion implantation is used to destroy superconductivity in the facing region without interrupting the lattice structure in the facing region, Further comprising a second flat HTS layer deposited and patterned on the central region and including two opposing regions abutting the central region and using ion implantation to block the lattice structure of the opposing region. High temperature superconducting current collector characterized in that the superconducting property of the opposite region is destroyed without being used, and further comprising a third HTS layer deposited and patterned on the second HTS layer. Circuit. 2. The central region of the second HTS layer comprises:
A contact is formed between the first and third HTS layers.
A multi-layer planar high-temperature superconducting integrated circuit according to claim 1. 3. The facing region of the second HTS layer comprises:
The multilayer planar high temperature superconducting integrated circuit according to claim 2, which acts as a dielectric. 4. The multi-layer planar high temperature superconducting integrated circuit according to claim 1, wherein the third HTS layer is flat. 5. Annealing in the flat first HTS layer to correct ion implant damage,
The method of claim 1 activating a chemical bond between the implant species and oxygen in the facing region of the first HTS layer and minimizing outdiffusion of the implanted species from the facing region to the central region. Multilayer planar high-temperature superconducting integrated circuit. 6. The multilayer planar high temperature superconducting integrated circuit of claim 5, wherein annealing is performed on the planar second HTS layer. 7. The third HTS layer comprises a central region and two facing regions abutting the central region, and the third HTS layer is formed by ion implantation without interrupting a lattice structure of the facing region. The multilayer planar high-temperature superconducting integrated circuit according to claim 1, which destroys the superconductivity of the facing region. 8. A multi-layer planar high temperature superconducting integrated circuit formed on a substrate, comprising: a central region deposited and patterned on the substrate, and two opposing regions abutting the central region. 1 flat high temperature superconducting (HTS) layer, ion implantation is used to destroy superconductivity in the facing region without interrupting the lattice structure of the facing region, and the flat first HTS Annealing is performed in the layer to correct ion implant damage, activate the chemical bond between the implant species and oxygen in the facing region of the first HTS layer, and implant from the facing region to the central region. A second region that is deposited and patterned on the first HTS layer and that has a central region and two opposing regions abutting the central region. Further comprising a flat high temperature superconducting (HTS) layer, wherein ion implantation is used to destroy superconductivity in the opposing region without interrupting the lattice structure in the opposing region, The facing area acts as a dielectric and is deposited and patterned on the second HTS layer and further comprises a third flat HTS layer comprising a central area and two facing areas abutting the central area. And using ion implantation to destroy superconductivity of the facing region without interrupting the lattice structure of the facing region, and wherein the central region of the second HTS layer includes the first and third regions. High temperature superconducting integrated circuit, wherein a contact is formed between the central regions of the HTS layer of the. 9. The multilayer planar high temperature superconducting integrated circuit of claim 8 wherein annealing is performed on the planar second HTS layer. 10. A method of manufacturing a multi-layer planar high temperature superconducting integrated circuit on a substrate, comprising depositing and patterning a first planar high temperature superconducting (HTS) layer on the substrate. Of the central region of the HTS layer and two opposing regions contacting the central region are masked, and ion implantation is used to destroy the superconductivity of the opposing region without interrupting the lattice structure of the opposing region. Depositing and patterning a second flat HTS layer on the flat first HTS layer, masking a central region of the flat second HTS layer and two opposing regions abutting the central region. And then using ion implantation to destroy superconductivity in the facing region of the second flat HTS layer without interrupting the lattice structure in the facing region, and on the second HTS layer. A step of depositing and patterning a third HTS layer. 11. The flat second HTS layer and the third
11. The method of manufacturing a multi-layer planar high temperature superconducting integrated circuit of claim 10, wherein said HTS layer is epitaxially deposited on said planar first HTS layer. 12. The method of manufacturing a multi-layer planar high temperature superconducting integrated circuit of claim 10, wherein the central region of the second HTS layer forms a contact between the first and third HTS layers. . 13. The method of manufacturing a multi-layer planar high temperature superconducting integrated circuit according to claim 10, wherein the third HTS layer is flat. 14. The flat first HTS layer is annealed to correct ion implant damage, and the first first HTS layer is annealed.
Further comprising the step of activating a chemical bond between the implant species and oxygen in the facing region of the HTS layer and minimizing outdiffusion of the implanted species from the facing region to the central region. 11. A method of manufacturing a multi-layer planar type high temperature superconducting integrated circuit according to 10. 15. The method of manufacturing a multi-layer planar high temperature superconducting integrated circuit of claim 14 further comprising the step of annealing the planar second HTS layer. 16. A multilayer planar high temperature superconducting integrated circuit formed on a substrate, comprising: a central region deposited and patterned on the substrate, and two opposing regions abutting the central region. A flat high temperature superconducting (HTS) layer, using ion implantation at a first implant energy level to destroy superconductivity in the facing region without interrupting the lattice structure in the facing region, And using ion implantation at a second energy level lower than the first implant energy level to destroy superconductivity in the upper portion of the central region without destroying the lattice structure in the opposite upper portion of the central region, and Forming a contact and deposited and patterned on the first HTS layer to abut the facing region, the contact, and the top. That the second of H
A high-temperature superconducting integrated circuit further comprising a TS layer. 17. The second layer comprises a central region and two facing regions abutting the central region, and the second layer is formed by ion implantation without facing the lattice structure of the facing region. 17. The multilayer planar high temperature superconducting integrated circuit of claim 16 which destroys superconductivity in a region. 18. The first layer is flat.
7. The planar type high temperature superconducting integrated circuit described in 7. 19. A method of manufacturing a planar high temperature superconducting integrated circuit on a substrate, comprising depositing and patterning a first flat high temperature superconducting (HTS) layer on the substrate, the central region and the central region. Masking two opposing regions abutting the region and using ion implantation at a first implant energy level to destroy superconductivity of the opposing region without interrupting the lattice structure of the opposing region, Second lower than the first implant energy level
Energy levels of ion implantation to destroy superconductivity in opposite upper portions of the central region to form contacts without destroying the lattice structure above the central region, and the first HTS layer Above the first H
Depositing and patterning a second HTS layer to abut the opposing region of the TS layer, the contact and the top. 20. Masking a central region and two opposing regions abutting the central region in the second HTS layer,
20. The planar high temperature according to claim 19, further comprising the step of implanting ions in the facing region to destroy the superconductivity of the facing region without interrupting the lattice structure of the facing region. Method of manufacturing a superconducting integrated circuit. 21. The second layer is flat.
0. A method of manufacturing a planar type high temperature superconducting integrated circuit according to 0. 22. A planar high-temperature superconducting integrated circuit formed on a substrate, comprising: a first high-temperature superconducting (deposited and patterned on the substrate, including a lower portion having an opposing region abutting a central region). H
TS) layer, said counter-region being bombarded using ion implantation with high energy deep range ions to destroy superconductivity of said lower counter-region. High temperature superconducting integrated circuit. 23. The first HTS layer comprises an intermediate portion having an opposing region abutting a central region, the opposing region being bombarded using ion implantation with ions in the intermediate range of intermediate energies, 23. The planar high temperature superconducting integrated circuit of claim 22 wherein the superconductivity of the opposing region of the middle portion is destroyed and further comprising a top having a central superconducting region. 24. The upper portion has an opposing region that abuts the central region, the opposing region being bombarded using ion implantation with low energy, low range ions, the opposing region of the upper portion The planar high temperature superconducting integrated circuit of claim 23, wherein superconductivity is destroyed. 25. The planar type of claim 22, wherein the upper portion has an opposing region that abuts the central region, and the upper opposing region that abuts the central region is removed by etching. High temperature superconducting integrated circuit. 26. The planar high-temperature superconducting integrated circuit according to claim 22, wherein the high-energy high-range ions and the intermediate-energy intermediate-range ions have low dispersiveness. 27. A method of manufacturing a planar type high temperature superconducting integrated circuit on a substrate, comprising depositing and patterning a first HTS layer on the substrate and using a photoresist / mask to form the first HTS layer. A central region and an opposing region abutting the central region relative to the lower part of the first region, and bombarding the first HTS layer with ion implantation with high energy deep range ions, The method comprises the step of destroying superconductivity in the opposing region of. 28. A photoresist / mask is used to delineate a central region and an opposing region abutting the central region with respect to an intermediate portion of the first HTS layer, and with ions in an intermediate range of intermediate energies. 28. The planar high temperature superconducting integrated circuit of claim 27, further comprising the step of bombarding the first HTS layer using ion implantation to destroy superconductivity in the facing region of the middle portion. A method of manufacturing. 29. The method of claim 27, further comprising the step of using a photoresist / mask to contour a central region to the top of the first HTS layer and an opposing region abutting the central region. Method of manufacturing a planar type high temperature superconducting integrated circuit. 30. The first HTS using ion implantation with low energy, low range ions.
30. The method of manufacturing a planar high temperature superconducting integrated circuit of claim 29, further comprising bombarding the layer to destroy superconductivity in the upper facing region. 31. The method of manufacturing a planar high temperature superconducting integrated circuit according to claim 29, further comprising the step of etching the opposing region of the upper portion abutting the central region.