JPS5951549A - Manufacture of integrated circuit device - Google Patents

Abstract

PURPOSE:To form a flat inter-layer insulating film at low temperature without a high temperature heat treatment by etching a silicon film until the inter-layer insulating film at a high step-up part, thereafter forming a second inter-layer insulating film, opening a contact hole and then forming a second wiring material. CONSTITUTION:A first wiring layer 3 is formed and a silicon oxide film 4 is formed as the inter-layer insulating film. Thereafter, a polycrystalline silicon film or non-crystalline silicon film 5 is formed by growth method. In this case, a lower stepped part A is formed thicker than a high stepped part B utilizing a growth method having good step coverage. When thickness of silicon to be grown is set to 1/2 or more of the minimum interval C of the higher stepped part of the inter-layer insulating film. Thereby, the minimum interval part is perfectly filled. The silicon film at the part B is perfectly etched from the entire part by the plasma etching and the silicon film is left only at the lower stepped part A. Here, the inter-layer insulating film 6 is provided again and a contact hole is opened by the tapered etching only on the first wiring material layer, and thereafter a second wiring material 8 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing an integrated circuit device, and particularly to the formation of a flat interlayer R adjacent to the interlayer.

Generally, in integrated circuit devices, particularly in semiconductor integrated circuit devices, a metal film such as aluminum is used as a wiring material, but if the interlayer insulating film under the metal thin layer has a steep step, the metal wiring may break. , often. For this reason, a planarization technique for reducing and flattening the level difference in the interlayer insulating film is very important for fx.

In recent years, with the increasing use of fine processing of wiring materials and multilayer wiring, this planarization technology has become indispensable. In addition, due to the need for shallow pH junctions due to high integration, and the need to realize a multilayer wiring structure using low melting point gold stripes such as aluminum, technology for flattening the interlayer R film using high temperature heat treatment has been developed. It is no longer usable and requires planarization using a low-temperature process.

An object of the present invention is to provide a technique for planarizing an interlayer insulating film using a low-temperature process.

The features of the present invention include a step of forming a first interlayer insulating film on the first layer of wiring material, a step of growing a polycrystalline silicon film or an amorphous silicon film on the interlayer insulating film,
The silicon film is etched until the first layer of interlayer insulation in the portion with severe steps is exposed, and then a second interlayer insulation film is formed:
and forming a contact hole only on the wiring material to form a second wiring material. Preferably, the silicon layer is grown by 1° or more than half the minimum spacing between the remaining steps of the interlayer insulation layer.

The technique for planarizing interlayer insulation according to the present invention will be described below using examples.

In FIG. 1, a silicon oxide film 2 is formed on one main surface of a silicon substrate 1, a first layer of wiring 3 is formed thereon, and a silicon oxide film 4 is grown as an interlayer insulating film.

Thereafter, a polycrystalline silicon film or an amorphous silicon film 5 is grown as shown in FIG. Here, as for the growth method of the silicon film, if a growth method with good step coverage is used, such as sputter deposition method, plasma growth method, low-pressure low-temperature vapor phase growth method, etc., the lower part A of the step as shown in this figure can be
It is formed thicker than the higher part B. Also, if the first layer wiring material has a high melting point, such as polycrystalline silicon, molybdenum, tungsten, titanium, tantalum, etc.
Silicon films can be grown by normal vapor phase growth. If the growing silicon brittle J9 is grown to half or more of the minimum spacing C between the high steps of the interlayer insulation III, the minimum spacing will be completely filled and the second layer wiring will be formed. There will be no more disconnections.

Next, the silicon film 5 on the entire surface was etched by Prisma etching, with the aim of completely etching the tl (tl) of B. It is left only in part A. Here, 71J and interlayer insulating film 6 are grown by vapor phase epitaxy, plasma growth, sputter deposition, etc., as shown in Fig. 4.
It! Conductivity between the J-th wiring material and the second layer wiring material is 111.
! The contact hole for the connection may be formed only on the first layer wiring pattern by taper etching, as shown in FIG. After that, a second wiring material 8 was formed, as shown in FIG.

As described above, according to the present invention, it is possible to form a flat interlayer insulating film at a low temperature without undergoing high-temperature heat treatment, and it is very effective for high integration and multilayer wiring.

[Brief explanation of drawings]

1 to 6 are sectional views of embodiments of the present invention. In addition, in 71, 1... silicon substrate, 2...
...Silicon oxide film, 3, 8... Wiring material, 4, 6... Interlayer insulating film, 5... Silicon film, 7... It is a contact hole. 1st figure hand 2 Ding 3rd figure 4 figure 5 Koku 6 concave

Claims (2)

[Claims] (1) A method for manufacturing an integrated circuit device, including the step of forming a first glabella insulating film with a step on its surface, and growing a polycrystalline silicon film or an amorphous silicon film on the first interlayer insulating film. a step of etching the silicon film until the first interlayer insulation film in the high step portion reaches νN, and then forming a second interlayer insulation film; 1. A method for manufacturing an integrated circuit device, comprising the step of forming a wiring layer. (2) Manufacture of an integrated circuit device according to claim (1), characterized in that the silicon film is grown by 1/2 of the minimum interval between the high steps of the interlayer insulating film or more. Method.