JPH01500550A - Method of manufacturing self-aligned MESFET - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Manufacturing method of self-aligned 1EsFET Attack 4 divisions The present invention provides a method for self-aligning the gate of MEESFET: Ru.

1! Techniques Self-alignment technology’%1. Conventional 10SFET technology is routinely used.

The conventional technology has been referred to as silicon gate technology. However, l1l-l~Vi The use of compounds poses different problems than those associated with silicon technology. Example: i, IIL1-8'y: The annealing process in the manufacture of compound semiconductors involves the evaporation of elements. generally requires a cap to prevent In the manufacture of potassium arsenide devices, arsenic To prevent evaporation of the substance and keep the stoichiometry (stoichiometric ratio) of the substance constant. Caps are commonly used.

Implementation of self-alignment technology Be built. Ion implantation is then performed to form highly conductive regions for the source and train. to be accomplished. During this ion implantation process, the gate protects some areas from the gate implant. Acts as a mask. Therefore, the highly conductive source and drain regions are It extends to the region directly below the region to reduce the resistance between the source and the source. after that, An anneal cap is attached and the sample is annealed for activation of the implanted ionic species. Nealed. After removing the annealing cap, another manufacturing process is performed to A vise is made.

In the manufacture of semiconductor devices, controlling gate length is extremely important.

Transistor performance: is strongly influenced by the length of the t-gate, so the circuit Performance depends on gate length. The channel length below the semiconductor gate is only It is highly desirable to make it very long. Channels that are too long will result in a game break. This is because the down voltage is reduced. It also reduces leakage current between the gate and channel. Along with the It is also desirable to reduce the volume t.

Traditionally, a dummy gate is deposited on top of the silicon dioxide layer on top of the channel region of the substrate. I was in Sazzl. In other words, part of the silicon dioxide layer is removed using etching technology. Before long, two layers of aluminum (on top of the hissilicon layer) were deposited. The dummy gate consists of an aluminum cap with a silicon dioxide layer deposited on top of it. It has a structure that has It is then applied as a mask to protect the channel from ion implantation. Ion implantation was performed on the wafer using Lumicap. Then the dummy gate An undercut was formed under the aluminum mask. This process In this case, after removing the dummy gate, there is a gate metal in the remaining space. Since the metal is deposited, the final metal length should be shorter than the channel length. I'll come.

Before performing high temperature annealing, peel off the aluminum cap and apply an annealing cap. This prevents the release of arsenic (TJ) in the gallium bironide dioxide film.

However, with this method, the undercut work cannot be controlled sufficiently, so the gate length It is impossible to reliably control the uniformity of the thickness.

Furthermore, since the gate structure becomes uneven, the aluminum grain size becomes too large and the sub- Micron geometry; this is not suitable. Also, silicon dioxide annealing cap Removal of the aluminum gate mask after applying the mask: chemical etching Difficult to do. Gate length strongly affects FET performance, so It is difficult to control circuit performance unless the length of the circuit is consistently uniform. .

US Pat. No. 4, issued to Schuermeyer on August 6, 1985. 532. According to Ci95, titled "Method for fabricating self-aligned IGFET", nitriding ICs on a gallium arsenide wafer coated with a layer of silicon and a layer of silicon dioxide A FET is formed. The silicon dioxide in the transistor area is etched away and the The on-implant provides doping for the channel. Gate made of heat-resistant metal such as molybdenum is applied and contoured. This gate and silicon dioxide are connected to the source and drain. Functions as a mask for ion implantation.

No dummy or surrogate gates are used to control gate length.

U.S. Patent No. 4,472 issued September 25, 1984 to Toyoda et al. , No. 872, entitled "Method for manufacturing Schottky gate field effect transistor". If so, on the semiconductor substrate; forming Ml and a second stack facing each other; A Schottky gate FET is manufactured by Each stack has an ohmic It consists of poles and a spacer film. Both stacks have a base formed on top of them. An insulating layer is formed on the board in the thickness direction until the brainer surface is exposed. etched anisotropically along the As a result, part of the insulating layer is It remains on the opposite wall. Remove the spacer film and define a step in the opening of each remaining and each electrode. After that, a layer of metal material is formed that can form a Schottky barrier with the substrate. It will be done. The remainder is then removed and the layer of metal material is patterned. Form a Schottky gate electrode.

且匪小板ふ The present invention provides an improved method for making semiconductor devices. In other words The present invention provides an alternative method with sidewall structures to mask the channel region during the ion implantation process. A method using gates is provided.

The method comprises depositing a layer of insulating material on a surface of a support substrate.

The substrate includes a channel region below the surface having a carrier concentration of the desired conductivity type.

Selected portions of the insulating material are removed and a substitute gate is formed on the substrate surface. substitute gate Sidewalls are formed that interface with the surrogate gate to define an effective mask area that cooperates with the surrogate gate.

Ion implantation over unmasked areas and dopants into unmasked areas of the substrate implant to provide no channel doping in the desired region. remove side wall , the resulting device is annealed to activate the dopants in the substrate. Substitute game Gate metal is removed and gate metal is deposited in the space left after gate removal. control the length of the route. The length of the metal gate is the same as the substitute gate, while the length of the metal gate is the same as the substitute gate. The length of the channel is equal to the sum of the surrogate gate and sidewall. Gate length of channel It is highly desirable to make it longer than the length.

The first and second ohmic contacts are deposited on the substrate in the correct positional relation to each other, and Interconnect metals are deposited in electrical continuity with ohmic contacts to create semiconductor devices. make

The supporting substrate preferably contains semi-insulating gallium arsenide, but other 11i1- It can also be a group compound or silicon. The insulating material can be silicon dioxide, The sidewalls can also be formed of silicon nitride, polymer or photoresistor. n type toe The gate and sidewalls act as a mask while the -type implant species are implanted. , to prevent ion implantation directly under those masked regions. Removal of side walls is done by This is done by etching or reactive ion etching. This method is complete To achieve this, brainerized materials such as overpressure polymers and photoresists are It is applied as a conformal layer over the surface and the surrogate gate and is etched to expose the surrogate gate. After being tested back, the surrogate gate is removed by applying buffered hydrofluoric acid. Ru. Brainer 1 (3 materials are the top of the brainerized material structure, the bottom of the structure and the substrate) form the desired angle between the surfaces according to the contour of the surrogate gate.

This undercut is the area where the surrogate gate is removed. Limits the shape of the base metal. The remaining steps in the method include manufacturing semiconductor devices. This is standard in the construction field.

Other advantages and features of the invention will become apparent from the description below.

Figure □ Surface m-order plate The present invention will be described in more detail below, and the claims, which are considered novel, will be described in more detail. Describe. The invention is best understood by referring to the accompanying drawings below. Let's try: FIG. 1 is a side sectional view of a field effect transistor manufactured according to the present invention; and FIG. 2 shows typical steps in manufacturing the 7-IESFET of the present invention.

#LtJI Gomushigo 1Ω carving shop See Figure 1! lZ Then, the field effect transistor 10 manufactured according to the present invention is the indication. As shown in the figure, the transistor IO is made of semi-insulating gallium arsenide, Synthetic materials such as silicon and indium phosphide, or glass, single crystal silicon, and consisting of any of the above films applied on the top surface of another substrate such as steel or stainless steel. It is formed on a substrate 12 of semiconductor material. Substrate 12 has a surface 14, the surface below the carrier concentration of the desired conductivity type, such as n, n'', n-1p or p10. It includes a channel region 16.

A gate 22 is attached on the base Fi12, and a portion from #418 of the channel to the gate is attached. In order to reduce the breakdown voltage at the gate by increasing the separation]6, Gate 22 has a gate length of controlled dimensions. The gate 22 is connected to the substrate 12. A channel region J6 is formed close to the interface, and a relatively high phase in the transistor IO is formed. It acts to make it possible to achieve mutual conductance. Top of board 12: Inn 24 and source 26 are located.

The insulating material used for the substitute gate is preferably silicon dioxide or photoresist. However, aluminum nitride, aluminum oxide, tantalum oxide, titanium oxide, tungsten oxide, Gallium oxide, arsenic oxide, molybdenum oxide, oxynitride, gallium arsenic oxide, oxide Aluminum gallium arsenide, indium gallium arsenide phosphorus, and indium oxide It can also be a compound selected from the group consisting of:

Gate 22: Generally, a multilayer structure made of a single heat-resistant material such as platinum or gold. It is. Gate 22 is attached directly to the top of substrate 12. Moreover, on the substrate 12, A doin 24 of ohmic material is deposited to serve as a drain electrode.

Similarly, the source 26, which is made of ohmic material, is connected to the drain 2 with respect to the gate 22. 4 and is attached on the substrate 12 on the opposite side. The drain 24 and source 26 are aluminum, molybdenum or molybdenum-tantalum alloy, chromium, titanium, tungsten It may be formed of any suitable ohmic material, such as copper, palladium, and platinum. Like Alternatively, the ohmic material is gold-germanium. Also drain 24 and source 26 is an ion implantation region having carrier conductivity of the desired conductivity type, preferably no. Including area. Both drain 24 and source 26 are self-aligned to gate 22. Ru. A metal interconnect 28 is deposited on top of both train 24 and source 26. , which serves as the electrical connection for the current conducting path in the transistor.

Referring now to FIG. 2, representative steps of the method of the present invention are illustrated.

Regions below the surface of the substrate are ion-implanted and filled with a chip containing a carrier concentration of the desired conductivity type. After forming the channel, it is annealed at a high temperature of about 800-850℃ for 7 hours to form the ion implantation area. Activate the area. A layer of insulator is then deposited onto the substrate and selectively etched away. The remaining layer is used as a substitute gate. Substitute gate insulation material! Adhesion of 4; yo, any Can be done using standard deposition techniques.

After forming the substitute gate, silicon dioxide, silicon nitride, polymer and photo A conformal sidewall N of a dielectric material selected from the group consisting of resist and sidewalls are formed on the surrogate gate by depositing on the surrogate gate. Squirting Then, try etching is performed to form the side wall. Side wall material is from substitute gate material Selective etch removal is much faster, i.e., on the order of 20-1. Therefore, it is preferable to preferentially use reactive ion etching. reactive io The method of etching reduces the thickness of the sidewalls to approximately 0.05 to 0.3 microns, preferably Reduce thickness to 1500-2000 angstroms. The side wall thickness is Determine the distance between the port and the ends of the channel.

After forming the sidewalls, ion implantation is performed by implanting n-type implanters. The substitute gate and sidewalls prevent ion implantation directly below and in the immediate vicinity of the substitute gate. Give a mask. This ion implantation process creates an irregularly spread n-region sidewall structure. A channel formed by slight erosion into the area below the structure and longer than the length of the surrogate gate. give length.

After ion implantation, try etching, preferably reactive ion etching or plastic The side wall is removed by Zuma etching, leaving a substitute gate.

Instead of covering the entire structure with a cap to prevent evaporation from within the substrate, Capless annealing is performed in an overpressure arsenic environment at high temperatures. this annie under an overpressure of about 0.010 to about 0.10 atmospheres of arsenic, about 750 to 12 Be done at 00°C. Also, annealing is performed in an environment of a complex gas containing at least arsenic. It can be done for about 10 seconds to 60 minutes. It is preferable to anneal for about 20 minutes. Delicious. After annealing, a block selected from the group consisting of polymer and photoresist is Unfortunately, the rayonization material stains both the substrate surface and the substitute gate. This blur The dielectric material is etched back to expose the substitute gate. Substitute gate exposed Once completed, apply buffered hydrofluoric acid to remove the surrogate gate. This is it The planarization has a desired angle between the top of the structure, the bottom of the structure, and the surface of the substrate. A structure of material is formed. Next, make an undercut, preferably about 756 to 90 degrees. or form an angle between 80° and 85°. Gate metal after substitute gate A shape of amp-cut brainerized material is deposited and cut into the remaining space. Therefore, the undercut above facilitates the removal of the substitute metal and later Limit the shape of the gate material deposited. Adhesion of gate material is limited to platinum or gold. and a refractory material, conformal to the entire surface of the substrate.

The brainerized material is then peeled off along with the gate material deposited thereon; Leave only the gate metal attached to the top of the substrate. Next is the ohmic contact , is deposited on the area left unmasked by the substitute gate. And phase An interconnect metal is deposited on the ohmink contact to conduct electricity through the transistor. give a way Additionally, additional conventional techniques are applied to incorporate the semiconductor device I\. Complete the transistor.

Although the best cedar condition for carrying out the invention has been explained in detail above, fields related to this invention A person skilled in the art will be able to carry out the invention as limited by the scope of the following claims. Alternative species and embodiments could be considered.

Engraving (no changes to the content) Clean H (no change in content).

Yoshi, Commissioner of the Patent Office 1) Takeshi Moon 1. Indication of case PCT/US 871013542, title of invention Self-consistency MESFET manufacturing method 3, person who makes the correction Relationship to the case: Applicant international search report

Claims (1)

[Claims] 1. (Correction) In a method of manufacturing a semiconductor device: a. has the back side and the desired on a support substrate containing a channel region below a surface with a carrier concentration of a conductivity type; depositing a layer of insulating material on; b. Remove selected portions of the insulating material and remove the substrate surface. forming a substitute gate on top; c. of the group consisting of silicon dioxide, silicon nitride, polymers and photoresists. forming sidewalls of dielectric material surrounding the surrogate gate, limiting the effective mask area to cooperate; d. reduce the sidewall thickness to the desired thickness; e ．． ion implanting a dopant into unmasked regions of the substrate; f. excluding side walls leave; g. Annealing the resulting device; h. Brainer on the substrate surface and substitute gate After applying the polymeric material, the polymeric material is etched back to form the top of the substitute gate. exposing; i. Remove substitute gate; j. Place the gate metal and the first and second ohmic contacts on the board in the correct position relative to each other. adhere to; and k. Deposit interconnection metal in electrical continuity with the electrical contacts and attach the semiconductor device. A method comprising: producing; 3. Claim 1, wherein the support substrate comprises a semi-insulating gallium arsenide material substrate. How to put it on. 4. The method of claim 1, wherein the support substrate comprises an indium phosphide substrate. 5. 2. The method of claim 1, wherein the support substrate comprises a silicon substrate. 6. The insulating material is silicon dioxide, silicon nitride, aluminum nitride, aluminum oxide. , tantalum oxide, titanium oxide, tungsten oxide, gallium oxide, oxidized waste, acid Molybdenum oxide, oxynitride, gallium arsenide oxide, aluminum gallium arsenide oxide, ion oxide selected from the group consisting of indium gallium arsenide phosphorous and indium oxide phosphorus. 2. The method according to claim 1, wherein the method is a synthetic product. 7. The sidewall formation involves depositing sidewall material on top of the insulating layer and then reactive ions. This is done by applying an etching process to reduce the sidewall thickness to the desired thickness. The method according to claim 1. 8. The reactive ion etching step reduces the sidewall thickness to approximately 0.05-0.3 mm. 8. A method according to claim 7, wherein the thickness is reduced to a thickness of 100 mm. 9. Forming the sidewalls deposits a precisely applied and easily removable dielectric material. The method according to claim 1, which is performed by. 10. The dielectric materials include silicon dioxide, silicon nitride, polymers and photoreceptors. 10. The method of claim 9, wherein the method is selected from the group consisting of: 11. The ion implantation is performed by ion implanting an n-type implantation species; Request for a substitute mask to provide a mask that prevents ion implantation directly under the substitute mask area The method described in item 1. 12. Claim 1, wherein the sidewall is removed by dry etching. How to put it on. 13. Removal of the sidewalls is done by reactive ion etching, and the sidewall material is The material according to claim 1, which is removed at a much faster rate than the material of the substitute gate. Law. 14. Claim 1, wherein the annealing is capless annealing performed at a high temperature. The method described in Section 1. 15. Claim 14, wherein said annealing is performed at about 750-1200°C. the method of. 16. the annealing is conducted under an overpressure of about 0.01 to about 0.10 atmospheres of arsenic; The method according to claim 1. 17. The annealing is performed in a complex gas environment containing at least arsenic. The method described in Scope 1. 18. The method of claim 1, wherein the annealing is performed for about 10 seconds to 60 minutes. Law. 19. 19. The method of claim 18, wherein said annealing is performed for about 20 minutes. 20. Brainerized materials selected from the group consisting of polymers and photoresists. The brainerized material is applied as a conformal layer on the surface of the substrate and on the surrogate gate in an etch bath. 2. The method of claim 1, further comprising: exposing the surrogate gate by exposing the surrogate gate. 21. Claim 1, wherein the removal of said substitute gate is done using buffered hydrofluoric acid. The method described in Section 1. 22. Brainer with desired angle between the top of the structure, the bottom of the structure and the surface of the substrate The method further comprises forming a structure of the substituted material to obtain the contour of the substitute gate. 21. The method according to claim 20. 23. of claim 1, wherein said undercut is made to form about 75° to 90°. The method according to scope item 22. 24. The gate metal is attached to the entire surface of the substrate, which has a multilayer structure including a heat-resistant material. 2. The method of claim 1, wherein the method is carried out by conformal deposition. 25. In a method of making a semiconductor device: a. has a surface with n-type conductivity. on a gallium arsenide support substrate containing a channel region below the surface with a carrier concentration , a layer of silicon dioxide is applied approximately 4000 to 15,000 angstroms thick. put on; b. Remove selected portions of silicon dioxide and place substitute gates on the substrate surface. form; c. A layer of silicon nitride was deposited approximately 2000 angstroms thick to create a substitute game. Form a sidewall surrounding the base plate, and remove selected portions of the sidewall by dry etching to remove ions. forming sidewalls of sufficient thickness to block injection; d. Board not masked ion-implanting an n+ type dopant into the region; e. Reactive ion etching preferentially sidewalls without etching substitute gates removing sidewalls from the substitute gate by; f. To prevent arsenic evaporation, approx. Capless annealing at 800°-900° under arsenic overpressure for approximately 2 minutes do; g. removing the surrogate gate by applying buffered hydrofluoric acid to the surrogate gate; h. Place the gate metal and the first and second ohmic contacts on the board in the correct position relative to each other. adhere; and i. Deposit interconnection metal in electrical continuity with the electrical contacts and attach the semiconductor device. A method comprising: producing;