JPH05341739A - Screen dividing device - Google Patents

Abstract

PURPOSE:To constitute a device with simple constitution and at a low cost and to set the number of division in the horizontal direction and in the vertical direction optionally. CONSTITUTION:Plural switches S1-S4 are provided corresponding to respective monitors and respective parts of displayed on respective monitors among input video signals are selected and taken out. By a switching control circuit 33, a switching control signal for indicating the selective taking out of the video signal to plural switches S1-S4 from a horizontal and a vertical synchronizing signals multiplying the horizontal and the vertical synchronizing signals of the input video signals respectively is generated. By a synchronizing signal branching circuit 34, the multiplied horizontal and vertical synchronizing signals are branched and timing adjusted and supplied to plural monitors.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a screen dividing device.
The present invention relates to a screen division device that divides and displays a screen image on a plurality of screens.

[0002]

2. Description of the Related Art FIG. 8 shows a block diagram of an example of a conventional device. The analog video signal coming into the terminal 10 is digitized by the AD converter 12. The sampling clock used in this AD converter is generated in the clock generation circuit 13 based on the synchronization signal from the terminal 11. The digitized video signal is supplied to the frame memories 14 _{1 to} 14 _4, and according to the write address from the write address generation circuit 15, the frame memory 14 ₁ is divided into two parts in the horizontal and vertical directions. The digital video signal of the upper left portion is written, and the frame memories 14 ₂ , 1
Digital video signals of the upper right portion, the lower left portion, and the lower right portion are written in 4 ₃ and 14 _{4 respectively} .

A digital video signal is read from each of the frame memories 14 _{1 to} 14 _{n according} to the read address from the read address generating circuit 16, and the D / A converter 1 is read.
It will be analogized from 7 _{1 to} 17 ₄ . The sync signal and read clock generation circuit 18 supplies the sync signal to the read address generation circuit 16 and the read clock to the D / A converter. The D / A converters 17 ₁ to 17 ₁
Each of the video signals 7 ₄ is converted into an analog video signal by using the read clock and is supplied to each of the monitors 20 _{1 to} 20 ₄ . Monitor 2
Each of 0 _{1 to} 20 ₄ displays an analog video signal supplied in synchronization with the sync signal and the sync signal from the read clock generation circuit 18.

[0004]

Since the conventional apparatus stores the digital video signal in the frame memory, the A / D converter 12 and the frame memories 14 _{1 to} 14 ₄ and D are stored in the frame memory.
/ A converter 17 ₁ to 17 ₄ and requires expensive circuitry, there is a problem that the apparatus becomes expensive.

Further, it is preferable to divide the screen into two in the horizontal direction and the vertical direction, but in the case of dividing into three or five, the pixel to be displayed is generated by digital calculation of the pixels adjacent to it. Then, it becomes necessary to interpolate and display, a digital operation circuit for this is required, and the circuit configuration becomes complicated.

The present invention has been made in view of the above points,
It is an object of the present invention to provide a screen dividing device which has a simple structure and can be inexpensively constructed, and which can arbitrarily set the number of divisions in the horizontal and vertical directions.

[0007]

A screen splitting device of the present invention is a screen splitting device that splits and displays an image for one screen on a screen of a plurality of monitors and is provided corresponding to each monitor. A plurality of switches for selecting and extracting respective portions of the input video signal to be displayed on each monitor, and horizontal and vertical synchronization obtained by multiplying the horizontal and vertical synchronization signals of the input video signal by the number of divisions in the horizontal and vertical directions respectively. A switching control circuit that generates a switching control signal for instructing the plurality of switches to selectively extract the video signal from the signal, performs branching and timing adjustment of the multiplied horizontal and vertical synchronization signals, and supplies them to the plurality of monitors. And a synchronizing signal branch circuit.

A decompression circuit for decompressing the time axis of the analog input video signal, and a plurality of parts which are provided corresponding to the respective monitors and which select and display respective parts of the decompressed video signal to be displayed on the respective monitors are taken out. A switch, a switching control circuit that generates a switching control signal for instructing the plurality of switches to selectively extract the video signal based on the horizontal and vertical sync signals of the input video signal, and the horizontal and vertical sync signals. And a synchronization signal branch circuit that performs branching and timing adjustment and supplies the plurality of monitors to the plurality of monitors.

[0009]

In the present invention, an analog video signal is divided by a switch corresponding to a monitor, selected, and simultaneously, a synchronizing signal is multiplied in the horizontal and vertical directions, and the timing is adjusted and supplied to the monitor. There is no need to digitize the signal and store it in the frame memory, the circuit configuration is simple and inexpensive, and the video signal is simply switched. Therefore, the number of divisions in the horizontal and vertical directions can be arbitrarily selected. The basic configuration is the same.

Further, by expanding, dividing and selecting the video signal, the horizontal scanning period of the horizontal scanning monitor can be increased and display on the current monitor becomes possible.

[0011]

1 is a block diagram of an embodiment of the device of the present invention.

In the figure, a terminal 30 receives a raster scanning type analog video signal as shown in FIG. 2A and is supplied to the terminals a of the switches S1 to S4. Switches S1 ~
The terminal b of S4 is fixed to the black level of the analog video signal (ground level in this case).

The synchronizing signal shown in FIG. 2B, that is, the horizontal synchronizing signal and the vertical synchronizing signal are input to the terminal 31, and the multiplier circuit 3
2 is supplied. The multiplication circuit 32 multiplies the repetition frequency of each of the horizontal synchronization signal and the vertical synchronization signal by two and supplies it to the switching control circuit 33 and the synchronization signal division circuit 34, respectively.

The switching control circuit 33 uses the multiplied horizontal and vertical synchronizing signals to generate four types of switching control signals and supplies them to the switches S1 to S4, respectively.
The first switching control signal supplied to the switch S1 becomes H level in the first half of the vertical scanning cycle before multiplication and becomes L level in the second half of the horizontal scanning cycle before multiplication.
The signal is as shown in (C). The second switching control signal supplied to the switch S2 is a signal as shown in FIG. 2 (F) which becomes H level in the latter half of the horizontal scanning cycle before multiplication and L level in the first half of the vertical scanning cycle before multiplication. is there. The third switching control signal supplied to the switch S3 is a signal as shown in FIG. 2 (C) which becomes H level in the first half of the horizontal scanning cycle before multiplication and becomes L level in the latter half of the horizontal scanning cycle before multiplication. is there. The fourth switching control signal supplied to the switch S4 is a signal as shown in FIG. 2 (F) which becomes H level in the latter half of the horizontal scanning cycle before multiplication and becomes L level in the first half in the latter half of the vertical scanning cycle before multiplication. is there.

Each of the switches S1 to S4 selects and takes out the signal at the terminal a when the switching control signal is at the H level, and selects and takes out the signal at the terminal b when it is at the L level. The video signals extracted by the switches S1 to S4 are supplied to the _four monitors 35 _{1 to} 35 _{4, respectively} . As a result, the video signals of the first half and the second half of each horizontal scanning cycle are taken out from the switches S1 and S2 respectively in the first half of the vertical scanning cycle before multiplication, and from the switches S3 and S4 respectively in the latter half of the vertical scanning cycle before multiplication. The video signals in the first half and the second half of each horizontal scanning cycle are extracted.

The synchronizing signal branching circuit 34 branches the multiplied horizontal and vertical synchronizing signals into four and then adjusts the timings respectively to rise at the rising timing of the horizontal synchronizing signal before multiplication shown in FIG. 2B. Figure 2 with the same timing
It generates a horizontal synchronizing signal shown in (E) monitors 35 _1, 3
5 ₃ to generate the horizontal synchronizing signal shown in FIG. 2 (H) whose falling timing coincides with the falling timing of the horizontal synchronizing signal before multiplication and supply it to the monitors 35 ₂ and 35 ₄ , and similarly. A vertical synchronizing signal whose falling timing matches the falling timing of the vertical synchronizing signal before multiplication is generated and supplied to the monitors 35 ₁ and 35 ₂ , and the falling timing matches the falling timing of the vertical synchronizing signal before multiplication. A vertical synchronizing signal is generated and supplied to the monitors 35 ₃ and 35 ₄ .

For this reason, when the video signal and the synchronizing signal coming into the terminals 30 and 31 are displayed on a single monitor, n lines (n is, for example, 525) are scanned as shown in FIG. 3 (A). When the display line is formed is carried out, in the above embodiment the video make up one screen throughout as shown in FIG. 3 (B) on the monitor 35 _{1-35 4} is displayed. In this case, scanning lines 0 to n shown by solid lines are displayed. The scanning lines 0'-n 'indicated by broken lines are not substantially displayed because the switches S1-S4 select the terminal b and become black level.

In this way, the switches S1 to S4 are used to
Monitor video signal by dividing the video signal ₁~ 35_FourSupply to
The circuit configuration is extremely simple and inexpensive.
Becomes Also, the video signal is hardly distorted
It can handle color video signals as it is and is horizontal
The number of divisions in the vertical and vertical directions can be set arbitrarily
It In addition, if it is a raster scan type video signal, it is sequentially scanned and skipped.
It can be applied as it is regardless of overscan, and between the input and output of video signals
There is no delay. For color images, switch S
1 to S4 for each of the three systems of color video signals RGB
All you have to do is multiplying circuit 32 and switching control circuit 33.
And the synchronization signal branch circuit 34 can be shared.

FIG. 4 shows a block diagram of another embodiment of the device of the present invention. In FIG. 4, the video signal from the terminal 30 is supplied to the terminal a, and the terminals c are provided with switches S5 to S8 whose black level is fixed. Delay with switch S5
~ S8 A delay circuit 39 for supplying to each terminal b is provided. Further, the switching control circuit 36 uses the multiplied horizontal and vertical synchronizing signals to generate four types of switching control signals and supply them to the switches S5 to S8, respectively. The fifth switching control signal supplied to the switch S5 causes the terminal a to be selected in the first half of the vertical scanning cycle before multiplication and the terminal b to be selected in the latter half of the horizontal scanning cycle before multiplication, and the latter half of the vertical scanning cycle. Is a signal for selecting the terminal c. The sixth switching control signal supplied to the switch S6 causes the terminal a to be selected in the latter half of the horizontal scanning cycle before multiplication in the first half of the vertical scanning cycle before multiplication, and the terminal b in the first half to be selected in the latter half of the vertical scanning cycle. Is a signal for selecting the terminal c. The seventh switching control signal supplied to the switch S7 causes the terminal a to be selected in the first half of the horizontal scanning cycle before multiplication in the latter half of the vertical scanning cycle before multiplication, and the terminal b to be selected in the latter half of the horizontal scanning cycle before multiplication. Is a signal for selecting the terminal c. The eighth switching control signal supplied to the switch S8 causes the terminal a to be selected in the latter half of the horizontal scanning cycle before multiplication in the latter half of the vertical scanning cycle before multiplication, the terminal b to be selected in the first half, and the first half of the vertical scanning cycle to be selected. Is a signal for selecting the terminal c.

In this case, the video signal shown in FIG. 5 (A) is delayed by the time T to obtain FIG. 5 (B). Therefore, as shown in FIG. 5C, the video signal without delay is first extracted from the switch S1, and then the delayed video signal is extracted, and this is repeated alternately. Similarly, a video signal without delay and a delayed video signal are alternately taken out and output from the switch S2 as shown in FIG. 5 (D). Note that FIG. 5E shows the switching control signal of the switch S2.

Therefore, the same display as the scan lines 0 to n is displayed on the scan lines 0'to n'indicated by the broken line in FIG. 3B, and the number of scan lines involved in light emission is doubled, and the monitors 35 ₁ to 35 ₁ to 35
₄ , screen brightness is improved.

FIG. 6 shows a block diagram of another embodiment of the device of the present invention. In the same figure, FIG.
The analog video signals as shown in are switches S10 and S1.
It is supplied to each terminal a. Switching control circuit 4
7 is supplied with the synchronizing signal shown in FIG. 7B from the terminal 41, generates a switching control signal obtained by multiplying the horizontal synchronizing signal by two, and supplies the switching control signal to the switch S10 and also to the switch S11 through the inverter 43. As a result, the switch S10 takes out the video signal in the first half of the horizontal scanning cycle and supplies it to the decompression circuit 44 as shown in FIG. 7C, and the switch S11 outputs the video signal in the latter half of the horizontal scanning cycle as shown in FIG. 7E. Is taken out and supplied to the expansion circuit 45. The expansion circuits 44 and 45 respectively expand the time axis of the supplied video signal by a factor of 2 to output switches S12 and S13, S14 and S1 as expanded video signals shown in FIGS. 7D and 7F, respectively.
5 is supplied to each terminal a.

A switching control signal obtained by doubling the vertical synchronizing signal is supplied from the switching control circuit 42 to the switches S12 and S14, and the switching signal is supplied to the switches S13 and S15 through the inverter 46. Therefore, the switches S12 and S14 respectively take out the expanded video signals of FIGS. 7D and 7F in the first half of the vertical scanning period and output the monitors 3 from the terminals 47 ₁ and 47 _{2 respectively.}
5 ₁ and 35 ₂ and switches S 13 and S 15 respectively take out the expanded video signals of FIGS. 7D and 7F in the latter half of the vertical scanning cycle and monitor 35 ₃ from terminals 47 ₃ and 47 _{4 respectively} . Supply to 35 ₄ .

Also, shown in FIG.
The synchronizing signal is repeatedly multiplied by the vertical synchronizing signal by the multiplication circuit 48.
Only the wave number is doubled, then monitor 35 from terminal 49₁，
35 ₃To the synchronization signal together with the multiplication circuit 48.
A delay circuit 50 forming a signal branch circuit is shown in FIG.
And the monitor 35 from the terminal 51₂, 35_FourTo serve
Be paid.

The decompression circuits 44 and 45 digitize the supplied video signals by an AD converter, write them into two line memories at the same time, and alternately read out the digital video signals from the two line memories to set the time axis. It has a configuration in which it is doubled and converted into an analog by a DA converter.

In the case of a standard television image signal,
Horizontal scanning frequency 15.75 kHz Vertical scanning frequency 59.
94 Hz, and in the embodiment of FIG. 1, the monitors 35 _{1 to} 35
Each of the _four can use an ordinary commercial product with a horizontal scanning frequency of 31.5 kHz and a vertical scanning frequency of 120 Hz. However, the horizontal scanning frequency of the video signal generated by the workstation is 60 kHz or more, which is twice that of 120 kHz.
Horizontal scanning of z is difficult to achieve with ordinary commercial products,
In the embodiment of FIG. 6, the horizontal scanning cycle of each of the monitors 35 _{1 to} 35 ₄ is the same as the horizontal scanning cycle of the original video signal, so that it can be realized by an ordinary commercial product.

Further, in the embodiment of FIG. 6, the expansion circuits 44 and 4 are
The video signal is digitized in 5, but 2 in each circuit
It suffices to have only one line memory, the memory capacity is much smaller than that of the conventional frame memory, and the cost of the apparatus can be much lower than that of the prior art, if not as much as the embodiment of FIG.

[0028]

As described above, according to the screen dividing device of the present invention, the constitution is simple and inexpensive, and the number of divisions in the horizontal and vertical directions can be set arbitrarily, which is extremely practical. It is useful.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a device of the present invention.

FIG. 2 is a signal timing chart of each part of FIG.

FIG. 3 is a diagram for explaining the operation of the device of the present invention.

FIG. 4 is a block diagram of another embodiment of the device of the present invention.

5 is a signal timing chart of each part of FIG.

FIG. 6 is a block diagram of another embodiment of the device of the present invention.

FIG. 7 is a signal timing chart of each part of FIG.

FIG. 8 is a block diagram of an example of a conventional device.

[Explanation of symbols]

32 multiplier circuit 33 switching control circuit 34 synchronizing signal branching circuit 35 ₁ to 35 ₄ monitor S1~S15 switch

Claims (2)

[Claims] 1. A screen splitting device for splitting and displaying a video for one screen on a screen of a plurality of monitors, each portion being provided corresponding to each monitor and displaying on each monitor among analog input video signals. And a plurality of switches for extracting and outputting the video signals to the plurality of switches from the horizontal and vertical sync signals obtained by multiplying the horizontal and vertical sync signals of the input video signal by the number of divisions in the horizontal and vertical directions, respectively. A switching control circuit for generating a switching control signal for instructing the above, and a synchronizing signal branching circuit for branching and adjusting the timing of the multiplied horizontal and vertical synchronizing signals and supplying the same to the plurality of monitors. Screen splitting device. 2. A screen division device for dividing one screen of an image into a plurality of monitor screens for display, and an expansion circuit for expanding the time axis of an analog input video signal and a monitor provided corresponding to each monitor. , A plurality of switches for selecting and extracting respective portions of the expanded video signal to be displayed on each monitor, and selecting and extracting video signals to the plurality of switches based on the horizontal and vertical synchronizing signals of the input video signal. Screen division characterized by having a switching control circuit for generating a switching control signal for instructing, and a synchronizing signal branching circuit for branching and adjusting the timing of the horizontal and vertical synchronizing signals and supplying the same to the plurality of monitors. apparatus.