JPH01162088A - superimpose device - Google Patents

Abstract

PURPOSE:To obtain the superimpose image of high precision by providing a multiplexing means to output superimpose digital data instead of television picture data for graphic data from a data select means. CONSTITUTION:A superimpose circuit 18 selects and outputs the graphic data at a graphic data input time regardless of the input of the television picture data with priority and when the graphic data are not inputted, the television picture data are selected and outputted. Accordingly, from the superimpose circuit 18, the digital data, to which the graphic data are fit (multiplexed) in the television picture data, are removed and converted to an analog video signal (three primary color signal) by a D/A converter 21 of a next step. After that, the data are supplied through a prescribed signal processing circuit to a CRT22. Thus, the superimpose image is displayed by the CRT22.

Description

Detailed Description of the Invention [Summary] A superimposing device that superimposes a second image based on second three primary color signals onto a first image based on first three primary color signals. The purpose is to superimpose a high-definition graphic image using a CRT controller, each k dot (k is a natural number of 2 or more)
Graphic data generation means for reading graphic data based on 3/3 primary color signals in parallel, converting the graphic data from parallel to serial using a shift register, and outputting the parallel-to-serial conversion;
After converting the television signal into a digital signal using a sampling clock with a frequency that is 0 times the color burst signal frequency fsc (where n is a natural number of 2 or more), m dots are generated per horizontal scanning period (however, 2 m is a natural number, and m ＞
k) television image data generating means for obtaining television image data based on the three primary color signals, and supplying the CRT controller with a clock signal for operating the CRT controller at a cycle of an integer value most similar to m/k per horizontal scanning period; a clock signal generating means for generating a clock signal; a data selecting means for selectively outputting the output graphic data of the graphic data generating means so that the CRT controller operates equivalently at m/k cycles per horizontal scanning period; The apparatus further comprises multiplexing means for outputting superimposed digital data in place of the graphic data from the data selection means and the television image data.

[Industrial application field]

The present invention relates to a superimposing device, and more particularly to a superimposing device that superimposes a second image based on second three primary color signals onto a first image based on first three primary color signals.

Some television receivers and various other image display devices display characters 1 using three primary color signals supplied to external input terminals.
There is a known device with a superimpose function that inserts and displays images such as figures and symbols in place of part of the television image obtained by demodulating it inside the image display device. When performing such superimposition, it is necessary from the viewpoint of image quality that a high-definition image supplied from a personal computer or the like to the above-mentioned external input terminal can be displayed as is.

[Conventional technology]

2. Description of the Related Art An image generating apparatus having a configuration as shown in FIG. 5 is conventionally known as an apparatus for displaying high-definition graphic images on an image display device equipped with a CRT. In the figure, 1 is CR
T controller (hereinafter referred to as CRTC), 2 is memory,
3 is a shift register for parallel-to-serial conversion, and 4 is an output terminal.

The output signal of CRTCl is applied to the memory 2 as an address signal indicating graphic data to be displayed, and the graphic data is read out from the corresponding address. This graphic data is supplied to the shift register 3 via the data bus, where it is parallel-serial converted and then serially outputted to the output terminal 4. Furthermore, a synchronizing signal is added and supplied to the CRT, for example, 640 dots in the horizontal direction. , a graphic image of 400 vertical dots is displayed.

When trying to superimpose a graphic image from this CRTCI on television image data by digital processing, the above television image data has a color burst signal frequency fsc, which is a frequency often used in television line memories. Since a television signal sampled at 4fsc, which is four times the frequency, is used, there are 910 dots in one horizontal scanning period (63.56 μs). Furthermore, if the image display device to be displayed performs non-interlacing, the above sampling clock is further doubled in frequency at 8fs C (= 28y
63636 MHz) is used.

For superimposition, the dot clock of the graphic data (4-Yarakuta data) from CRT C1 and the dot clock of the above TV image data are 8 fs.
c It is necessary to avoid matching the phases, and for that purpose f'sc is the dot clock of the actual C RT C1.
Use.

On the other hand, for the above graphic data, in order to display the graphic image using a dot clock with a shorter cycle than the CRTCl clock, 8 dots of the graphic data are
They are read from the memory 2 in parallel in 1/2 cycle of the TCI clock, converted from parallel to serial by the shift register 3 as described above, and output serially as schematically shown by 5+, 52, . . . in FIG. . In addition, in Figure 6,
The diagonal line indicates the first dot (the same applies to other figures). Therefore,
In the above case, the memory cycle is 113.75 (=910÷8) in one horizontal scanning period (1H).

[Problem that the invention seeks to solve]

However, since the CRTCI cannot operate in fractional cycles, it is operated in 113 or 114 cycles per 1H. Therefore, in the case of 113 cycles, the dots displayed per day are 804 (= 113 x 8) dots, which is 6 dots short of the original 910 dots, as schematically shown in Figure 7 (A), while 11
In the case of 4 cycles, as schematically shown in Figure 7 (B), 91
912, which is 2 dots more than 0 dots (= 114 x 8
) becomes a dot.

Therefore, the above-mentioned shortage or excess of dots results in a shift in the display start position in the next scanning line, which is accumulated and ultimately results in an image that is gradually shifted to the left or right.

Therefore, conventionally it has not been possible to superimpose a high-definition graphic image and a television image by digital processing. In addition, if you want to force superimpose both of the above images, use the analog three primary color signals obtained by DA converting the graphic image data to the three primary color signals of the television signal.
Since this was done by multiplexing the primary color signals, in this case only a vertical resolution of 262.5 scanning lines of one field could be obtained, and a high definition image of 640 x 400 dots could not be obtained.

The present invention has been made in view of the above points, and an object of the present invention is to provide a superimposing device that can superimpose a television image and a high-definition graphic image based on CRTC.

[Problem that the invention seeks to solve]

FIG. 1 shows a block diagram of the principle of the present invention. In the figure, 7 is a CRT controller, 8 is a memory storing graphic data, and 9 is a shift register for parallel-to-serial conversion, which constitute a graphic data generating means 10. Further, 11 is a television image data generation means, 12 is a clock signal generation means, 13 is a data selection means, and 14 is a multiplexing means for outputting superimposed digital data.

The clock signal generating means 12 connects the CRT controller 7 to 1.
Operate at a cycle of an integer value closest to m/k per horizontal scanning period (where m is the number of dots of TV image data in one horizontal scanning period, k is the number of parallel output dots of the memory 8, and m>k). Generates a clock signal.

The data selection means 13 selectively outputs the graphic data from the graphic data generation means 10 so that the CRT controller 7 operates equivalently at m/k cycles per horizontal scanning period (one day).

[Effect]

Based on the address data from the CRT controller 7, graphic data of three primary color signals for k dots each is read out from the memory 8 and supplied to the shift register 9, where it is parallel-serial converted and then sent to the data selection means 1.
3.

The data selection means 13 switches the delay time and outputs graphic data so that the CRT controller 7 operates equivalently at m/k cycles per 1H.

On the other hand, the television image data generating means 11 generates the television signal by n times the color burst signal frequency fsc (however,
After converting into a digital signal using a sampling clock having a frequency (n is a natural number of 2 or more), m dots of television image data are generated per horizontal scanning period for each of the three primary color signals.

This television image data is output through the multiplexing means 14, but when graphic data is supplied from the data selection means 13 to the multiplexing means 14, only the graphic data is selectively output.

Here, TV image data is extracted at a rate of m dots per day, while graphic data is extracted from CRT.
Since the graphic data is obtained by the controller 7 operating equivalently with a dot clock of m/k period per 1H and is retrieved dot by dot from the memory 8, the dot clocks of both data match.

〔Example〕

FIG. 2 shows a block diagram of one embodiment of the invention.

In the figure, the same components as in FIG. 1 are given the same reference numerals. In FIG. 2, an analog color video signal taken out from a television signal source 15 is supplied to an A/D converter 16, where it is converted into a digital signal and then supplied to a digital decoder 17. Digital decoder 1
7 demodulates the digital color video signal converted with a 4fsc sampling clock into three primary color signals, and superimposes each of the three primary color signals in parallel as television image data with an 8fsc sampling clock when the CRT 22 uses a non-interlaced system. It is output to the circuit 18. However, television image data for each day is output for 910 dots for each of the three primary color signals.

On the other hand, the personal computer 19 creates a desired graphic image and supplies corresponding commands to the graphics generator 20 to generate graphic data. This graphic data is generated for each of the three primary colors: red, blue, and green.

The superimpose circuit 18 is a digital decoder 17
It has input terminals for both television image data and the above-mentioned graphic data, and when inputting graphic data, it selects and outputs graphic data with priority regardless of whether or not television image data is input. If not, TV image data is selectively output.

Therefore, digital data in which graphic data is embedded (multiplexed) in television image data is extracted from the superimpose circuit 18, and converted into an analog video signal (three primary color signals) by the D/A converter 21 at the next stage. After being converted, it is sent to the CRT2 via a predetermined signal processing circuit (not shown).
2. As a result, a superimposed image is displayed by the CRT 22. - As an example, the screen of this CRT 22 is a high-definition screen with 640 dots in the horizontal direction and 400 dots in the vertical direction.

Next, the configuration and operation of the main parts of the present invention will be explained in more detail with reference to FIGS. 3 and 4.

FIG. 3 shows a block diagram of one embodiment of a portion of the graphics generator 20 described above. In the figure, the same components as in FIG. 1 are denoted by the same reference numerals, and their explanations will be omitted. The circuit shown in FIG. 3 is provided for each of the three primary color signals.

In FIG. 3, 23 is a CRTC corresponding to CRTC 7 in FIG.

24 is a memory corresponding to the memory 8; 25 is a shift register corresponding to the shift register 9; and 26 is a timing signal generator corresponding to the clock signal generating means 12. Further, the shift register 27° data selector 28 and two select signal generators are connected to the data select means 13.
It consists of

The CRT 23 operates at 113 cycles per day (i.e., 910/
The integer values 114 and 11 that are closest to 8-113.75
113) of 3), and is also controlled by commands input from the personal computer 19 as necessary.

The output signal of CRTC23 is sent to memory 2 as an address signal.
4 to cause the graphic data at the desired address to be read. This graphic data is CRTC2
8 dots are read out in parallel per one period of operation of 3, converted into parallel to serial by the shift register 25, and serially supplied to the shift register 27.

FIG. 4 schematically shows the graphic data serially output from this shift register 25 for each line (scanning line), where the vertical numbers are line numbers and the horizontal numbers are the clock cycles of the CRTC 23. show. Also a1~
a525 indicates data at the beginning of a 525-tree line in one vertical scanning period (1V).

The shift register 27 is an 8-stage shift register having a serial input terminal and a parallel output terminal, and the signal line 1. The above graphic data is supplied to the data selector 28 via the output terminals 2°fl3 and 4.

The data selector 28 is a select signal generator to which the output signal of the timing signal generator 26 is supplied. Out of the four graphic data supplied via the signal lines 11+ to 4, the - Selectively output only graphic data.

That is, the data selector 28 receives the signal 1! at 1H of the first line. The graphic data input via fl 1 is selectively outputted, and the second line 1H selectively outputs the graphic data input via signal line 2.

Here, the graphic data of the signal line deficiency 2 is the signal line deficiency 1
The first data a1 of the first line of graphic data and the first data a2 of the second line of graphic data shown in FIG. They will be all together.

Thereafter, in the same manner as described above, the data selector 28 selects the signal line I13→f14→no1→no2→I2.3→... every day for the graphic data from the third line onwards. Switches and outputs graphic data input via the switch. As a result, the leading data a1 to a525 of the graphic data of each line are all aligned on a vertical line.

In addition, in the above embodiment, as shown by the broken line in FIG.
6 dots after 1113 cycles on the first line, etc., 4 dots after 113 cycles on the second line, 11 dots on the third line, etc.
Two dots after three cycles are used as a clock extension period, and the configuration is such that, for example, arbitrary data on that line is repeatedly output.

Therefore, some graphic data is output during the clock extension period described above, but only 640 dots are displayed on each line of the CRT 22 as described above, and during this clock extension period, horizontal blocks that do not appear on the screen of the CRT 22 are displayed. Since it is within the ranking period, there is no negative effect on the screen at all.

In this way, in this embodiment, the CRTC 23 is operated at an apparent upper 114 cycle during the 3H period, and then operated at 113 cycles during the next 1H period, which is alternately repeated, thereby increasing the average cycle for a certain period to 113. 75 and forcefully return it to the normal display position.

Note that if you do not use the data selector 28, etc. and absorb the shift equivalent to one vertical scanning period (=5258), the display position will shift by 2 dots for each line, so the shift register will be 1050. Dan (=
This is difficult to implement in practice because it requires a large-scale shift register (525x2 dots). In contrast, according to the present embodiment, the shift register 27 requires only eight stages.

Further, in this embodiment, 597118.
75 (= 113.75 x 525) periods, and since fractions still occur, the phase of the CRTC23 clock is forcibly switched within 1H during the vertical blanking period, as shown in Figure 4, and as a result, the final The phase is adjusted to match the dot clock of the TV image data.

It should be noted that the present invention is not limited to the above-mentioned embodiment, but it is also possible to operate the CRTC 23 at 114 cycles per 1H, and forcibly remove the deviation caused by this in the same manner as described above.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to match the dot clock of television image data and the dot clock of graphic image data obtained using CRTC, so that it is possible to superimpose both image data. Therefore, it is possible to obtain a superimposed image with higher definition than before. Furthermore, since the shift register and data selector are used together to absorb the shift equivalent to one vertical scanning period, the shift It has the advantage of being able to use an inexpensive and compact register with an extremely small number of stages.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the invention, Fig. 3 is a block diagram of an embodiment of the main part of the invention, and Fig. 4 is the operation of Fig. 3. Explanatory diagram, Fig. 5 is a block diagram of an example of the conventional main part, Fig. 6 is a block diagram of an example of the main part of the conventional
FIG. 7 is a diagram illustrating a shift in display position in a conventional device. In the figure, 7.23 is the CRT controller (CRTC), 8.24
9.25.27 is a shift register; 10 is a graphic data generation means; 11 is a television image data generation means; 12 is a clock signal generation means; 13 is a data selection means; 14 is a multiplexing means; 26 is a timing signal generation means. 28 is a data selector, and 29 is a select signal generator.

Claims (1)

[Claims] Based on the address data from the CRT controller (7), graphic data of three primary color signals for k dots (k is a natural number of 2 or more) is read out in parallel from the memory (8), and graphic data generating means (10) for parallel-serial converting graphic data using a shift register (9) and outputting the result; m dots per horizontal scanning period after converting to a digital signal using a sampling clock (however, m is a natural number, m>
m/m per horizontal scanning period;
A clock signal generating means (12) supplies the CRT controller (7) with a clock signal that operates at a cycle of an integer value closest to k, and the output graphic data of the graphic data generating means (10) is transmitted to the CRT controller. data selection means (13) for selectively outputting data such that (7) operates equivalently at m/k cycles per horizontal scanning period; Multiplexing means (14) for outputting superimposed digital data instead of data
) A superimposing device characterized by: