KR100416849B1 - A driving apparatus and method for PDP-TV - Google Patents

Abstract

The present invention relates to an appropriate signal processing for controlling input and output of digital image data in a PDP driving method of a plasma display panel television (PDP-TV).

In a typical PDP-TV system including a composite video signal input unit, a digital image data processing unit, and a PDP driving unit, the digital image data is rearranged in the memory unit in order to convert the digitized image data into a form suitable for PDP gray level processing. It rearranges the selected digital image data by using the main clock of the timing controller to select the data and outputs the data to the data interface unit. The data interface unit outputs the digital image data to the PDP driver in the form of a data stream suitable for gradation processing. It is.

The present invention focuses on the problem of requiring too many signals to shift data from the memory unit to the data interface unit, thereby generating one new reference signal instead of many data shift signals provided from the timing controller unit to the data interface unit. In addition, the present invention provides a method and a control apparatus for providing a data interface unit and generating a data shift signal in the data interface unit to control data input / output relations from the memory unit.

Description

A driving apparatus and method for PDP-TV

The present invention relates to an appropriate signal processing for controlling input and output of digital image data in a PDP driving method of a plasma display panel television (PDP-TV). In particular, the present invention relates to a method and apparatus for simplifying a signal system provided for input / output of digital image data of a memory unit and a data interface unit in an entire PDP-TV system.

The driving method of a flat panel display such as a PDP-TV is different from the driving method of a CRT. In particular, in the method of the gradation processing, the CRT adopts a method in which the electron gun sequentially scans the pixels one by one, and the gradation processing consists of a simple driving circuit driven by an analog method, and the driving speed is several tens of nanoseconds. sec) is very fast, but when the number of pixels is increased to millions such as HDTV, it is very difficult to implement the driving of millions of pixels by one pixel. However, in the case of PDP, a matrix driving method using strong nonlinearity characteristics of gas discharge is used instead of scanning pixel by pixel. Nonlinearity is a characteristic of gas discharge. Since the gas discharge phenomenon is caused by ionization through the ionization process of the gas, the discharge occurs only when a voltage higher than the discharge voltage at which the ionization reaction can occur sufficiently is applied. Is a characteristic of gas discharge in which no discharge occurs. PDPs are generally driven by a series of pulses with a constant voltage, and gradation display is implemented by digital rather than analog. Therefore, the whole PDP-TV system is operated with the configuration and operation for processing digital data.

In general, in the PDP-TV system, the digital image data is rearranged in the memory unit in order to convert the digitized image data including the composite image signal input unit, the digital image data processing unit, and the PDP driving unit into a form suitable for PDP gray level processing. It rearranges the selected digital image data by using the main clock of the timing controller to select the data and outputs the data to the data interface unit. The data interface unit outputs the digital image data to the PDP driver in the form of a data stream suitable for gradation processing. It is.

1 is an explanatory diagram for explaining signal processing for controlling the data input / output relationship between a conventional memory unit 1 and a data interface unit 2. FIG. In order to transfer data from the memory unit 1 to the data interface unit 2, one line is 853 × 3 (r, g, b), and 8 bits of R, G, and B are output from the memory. A signal of (853 x 3) ÷ [8 x 3 (r, g, b)] 107) is required. That is, since the timing controller 2 provides signals necessary for shifting the digital image data from the memory unit 1 to the data interface unit 2, the 107 signal output patterns and the data interface unit of the timing controller unit 3 are provided. Since 107 input patterns are required, a total of 214 patterns are required.

As described above, in the conventional PDP-TV driving method, an excessive signal pattern is required to control the digital image data input / output from the memory unit 1 to the data interface unit 2, which leads to a complicated and large system. There was this.

It is an object of the present invention to address the problem of requiring too many signal patterns in order to shift data from the memory section 1 to the data interface section 2, so that many data shifts are provided from the timing controller section to the data interface section. A new reference signal is generated instead of a signal and provided to a data interface unit together with a clock, and a data shift signal is generated by the data interface unit to control a data input / output relationship from a memory unit and a control device thereof.

1 is a block diagram of a conventional shift signal generating apparatus.

2 is an overall block diagram of a PDP-TV.

3 is a detailed block diagram of an essential part of FIG. 2;

4 is a block diagram of an apparatus for generating a shift signal for driving a PDP-TV of the present invention.

＊ Description of symbols on main parts of the drawings

10-AV unit 20-ADC unit

30-memory 40-data interface

50-Timing Controller 60-Address Drive IC

70-Hold / Scan Drive IC 80-High Voltage Drive Circuit

90-AC / DC converter 100-Analog composite video signal processor

200-Digital Data Processing Unit 300-PDP Driver

400-data rearranger 500-address generator

600-Control Clock Generator

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Accompanying drawings, Figure 2 is shown to explain a schematic overall configuration of the AC type PDP-TV system. The composite video signal received through the antenna is analog-processed by the audio-video (AV) unit 10 and digitalized by the analog-to-digital conveter (ADC) unit 20 with constant data. The image data is again provided to the address driver IC 60 in the form of a data stream conforming to the PDP gray scale processing characteristics through the memory unit 30 and the data interface unit 40.

In addition, the timing control unit 50 and the high voltage drive circuit unit 80 output the high voltage control pulses required by the sustain / scan drive IC 70, and the AC / DC change unit 90 uses the AC power as an input. Generate and supply all DC voltages required by the system. The overall configuration of the above PDP-TV system will be described in more detail for each block.

The AV unit 10 receives the NTSC composite signal, separates the analog R, G, and B signals from the horizontal and vertical synchronization signals, and obtains an APL (Average Picture Level) corresponding to the average value of the luminance signal (Y). Supplies). This APL is used to improve the brightness of PDP-TV systems. NTSC composite video signal is interlaced scanning method, and one frame is composed of two fields of Odd / Even, horizontal synchronous signal is about 15.73KHZ, and vertical synchronous signal is about 60Hz. The audio signal separated from the composite video signal is output through the audio amplifier directly to the speaker.

The ADC unit 20 receives analog R, G, and B signals as inputs, converts them into digital data, and outputs the digital data to the memory unit 30. At this time, the digital data has a converted shape to improve the brightness of the PDP-TV system. Video data. The ADC 20 is divided into an amplifier, a clock generator, a sampling area setting unit, and a data mapping unit.

In the ADC unit 20, the amplifier unit amplifies the analog R, G, B, and APL signals to a signal level suitable for quantization, converts horizontal and vertical synchronization signals into a constant phase, and outputs the same. The clock generator must use a clock that is synchronized with the input synchronization signal. To this end, the clock generator generates clocks using phase locked loops (PLLs). The PLL is oscillated by the LF (Loop Filter) that outputs the control voltage of PD (Phase Detector), VCXO (Voltage Controlled Crystal Oscillstor), and the control voltage. A VCXO and a PC (Programmable Counter) for dividing the output of the VCXO and outputting a phase comparison pulse to output a clock synchronized with the input synchronous signal. If the clock synchronized to the input synchronization signal is not used, the vertical linearity of the displayed image is not guaranteed. In addition, the sampling area is set to a vertical position and a horizontal position. The vertical position section is a pulse for setting only the line with the image information among the input signals, and the horizontal position section is a pulse for setting only the time with the image information among the lines set to the vertical position. The vertical position section and the horizontal position section are the standards for sampling. At this time, a total of 480 lines are selected, each with 240 lines in the Odd / Even field. The horizontal position section should be such that there can be at least 853 sampling clocks per selected line. The data mapping unit of the ADC unit 20 maps the R, G, and B data output from the A / D converter into data corresponding to the brightness characteristics of the PDP. In other words, by arranging several vector tables in the ROM and selecting the optimal vector table according to the digitized APL data, the R, G, The memory unit 30 is provided in the form of B data.

The memory unit 30 needs to reconstruct the video data of one field into a plurality of subfields for the PDP gradation process, and then rearrange from the most significant bit MSB to the least significant bit LSB. In addition, since the image data input by the interlaced scanning method is converted to the progressive scanning method and displayed, an area for storing one frame of image data is required.

3 is a block diagram of the memory unit 30 performing the above functions. That is, the memory unit 30 can be largely divided into the data rearrangement unit 400 and the address generator 500. The memory unit 30 is further composed of a control clock generator 300, two frame memories, and a data selector. The data rearrangement unit 400 is composed of shift registers A, B, D-FF & MUX. (D flip-flop and multiplexer), and three-state buffers A and B, and the ADC unit 20 has parallel (MSB to LSB). The video data provided by the rearranger is rearranged to be stored as bits having the same weight in one address of the frame memory. While the first shift register loads eight samples of image data, in the second shift register, eight samples of image data previously loaded are the least significant bit (LSB, 8) from the most significant bit (MSB, 8 Bits). Bits) are output while sequentially shifting.

In order to continuously rearrange video data provided by the ADC unit 20, two first and second shift registers are provided, and they alternately repeat load and shift operations. D-FF & MUX selects the same weighted data (Recordered Data) output in the shift mode and supplies it to the tri-state buffer. In addition, two frame memories are provided for storing one piece of image data (853 x 3 (RGB) x 480 x 8 Bits x 10 Mbit), and they alternately perform write and read operations in units of frames. The video data can be stored and displayed continuously. Therefore, the tri-state buffers A and B serve to connect the rearranged image data provided from the D-FF & MUX to the frame memory in the write mode.

Since the image data input by the interlaced scanning method is converted into a sequential scanning method and displayed, the order of writing addressing and reading addressing is different. Therefore, in the address generator 200, image data of one field stored in the memory is repeatedly read even line data after reading one line of Odd line data.

In addition, in the PDP gradation process, one field is divided into several subfields, and image data corresponding to each subfield must be read in turn and provided to the data interlacing unit 40, so that the reading order is structurally very different from the writing order. Will have Therefore, a write address generator and a read address generator according to the designed memory map configuration are required, and the address selector serves to provide a corresponding address according to each operation mode (write and read mode) of the frame memories A and B. The control clock generator 600 inputs the vertical and horizontal synchronization signals H and Vsync and the main clock to generate and supply the write / read address clock and all other logic control pulses required to drive the memory unit 30. . The data selector selects and outputs the image data output in the read mode among the frame memories A and B to the data interface unit 40. The data interlace unit 40 temporarily stores R, G, and B data from the memory unit 30 and provides the data in the form of data required by the address driver IC 60.

Arranged according to the R, G, and B pixel arrangements output from the memory unit 30 and supplied to the address driver IC 60, a data interface unit 40 is necessary. The display size is 853 × 3 (r, g, b) × 480, and the data interface 40 must temporarily store one line of data (853 × 3 = 2559 bits). Since the output must be performed simultaneously, two lines of temporary storage (2559 x 2 = 5118 bits) are needed.

In the data input / output process of the temporary storage area, a total of 24 bits of data of 8 bits each of R, G, and B are input to the temporary storage area A in turn (107 times) from the memory unit 30 (24 bits x 107 = 2598 bits). At intervals, data of one previous line of the temporary storage area B is output in the form of a data stream required by the address driver IC 60. Such input / output operations occur alternately in the temporary storage areas A and B. FIG. That is, after the temporary storage area A operates in the input mode, B operates in the output mode, and then, the operations in which A enters the output mode and B enters the input mode are repeated.

When outputting the temporarily stored image data to the address driver IC 60, the data interface unit 40 provides 1 bit of data and a total of 48 bits of image data to each driver IC in the form of a stream. When data is input to the address driver IC 60 in turn (75 times) in this manner, when shifted in parallel, one line (48 bits x 75 = 3600 bits) of image data is loaded into the address driver IC 60. Since this process should be the same as the input mode operation time of other temporary storage areas, the input mode should be operated at twice the frequency of the output mode.

The high voltage driving circuit unit 80 combines the DC high voltage supplied from the AC / DC converter 90 in accordance with the control pulses of various logic levels output from the timing controller unit 50, thereby maintaining the address, holding / scanning driving IC 70. The control pulse required by the C1) can be generated to drive the PDP. In addition, the data stream provided from the data interface unit 40 to the address driver IC 60 is also raised to an appropriate voltage level to enable selective writing on the panel. As described above, the driving method for the PDP gradation process first divides one field (60 Hz) into several subfields (64 gradations: 6 subfields, 256 gradations: 8 subfields), and then divides the image data corresponding to each subfield. The address is written to the panel in units of lines via the address driver IC 60. It is common to reduce the number of discharge sustain pulses in the order of LSB subfield in the subfield to which MSB data is written, and to perform gradation processing in the total discharge sustain period according to a combination thereof. In addition, the driving sequence of all subfields repeats operations of full screen writing and erasing, data writing, and discharge holding (screen display). This process is outlined as follows.

First, as the full screen erasing operation, the operation mode for erasing the discharge. In the case of AC PDP, the discharge is formed at a low voltage in the period of neutralizing the substitutive charge so that the wall charge is not sufficiently formed or the erase pulse having a short pulse width is removed. It removes the wall charge by preventing it from reaching the steady state. In order to erase the wall charge remaining in the selected (discharged) pixel after discharge sustaining of the previous subfield, the wall charge is written to all the pixels for a short period of time which is not visible, and then all the pixels are discharged. Thus, the PDP is initialized by erasing all remaining wall charges.

Secondly, the data writing and scanning operations are also referred to as selection operations. This is a driving operation necessary for initial discharge formation. In the case of penning mixtures of He + Xe and Ne + Xe, which are generally used in PDP, potential of 240Volt-280Volt is applied. In the case of AC, the third electrode is introduced to reduce the high current caused by the sustain electrode in the surface discharge form and the parasitic capacitor caused by the dielectric, and adopts a driving method that separates the selection operation from the sustain operation. In practical application, wall charges are selectively formed on pixels to be discharged by writing the data in line units through the data writing electrodes while shifting the scan pulses sequentially from 1 to 480 to the line scan electrodes.

Finally, as the discharge sustain operation, the sustain operation is a driving operation in which the discharge is maintained by a sustain pulse having a voltage lower than the selection pulse by using the storage function characteristic of gas discharge. In the case of AC PDP, the memory function effect by wall charge and the self priming effect are used in case of DC PDP. In the case of the memory type driving method which can separate the selection operation and the holding operation by using the memory function, in the case of high gradation display for realizing a high quality display device, the PDP can operate without deterioration of luminance even for a large display device. It provides a driving method.

In practice of the discharge sustain operation, a sustain pulse is alternately applied between the discharge sustain driver electrode and the line scan electrode to start and sustain the discharge of the pixel on which the wall charge is formed. At this time, since unwritten pixels are affected by the written peripheral pixels, and there is a possibility of causing an error discharge, a small erase is performed every time the sustain pulse is applied to ensure accurate discharge.

The AC / DC converter 90 generates and supplies the high voltage required to combine the electrode driving pulses with AC power (220V, 60Hz) and the DC voltage required by each component constituting the PDP-TV system. do.

Hereinafter, embodiments of the present invention will be described in detail. As described above, the digital image data input from the ADC unit 20 is rearranged in the memory unit 30 and selectively sent to the data interface unit 40, and the interface unit has an address driver IC 60 corresponding to the PDP driver unit. In the PDP-TV driving method for outputting data in the form of a data stream, one line is 853 x 3 (r, g, b) in order to transfer data from the memory unit 30 to the data interface unit 40. In the memory, 8 bits each of R, G, and B are output, so that 107 signals ((853 × 3) ÷ [8 × 3 (r, g, b)] # 107) are required at a time. That is, since the timing controller unit 50 provides signals necessary for shifting the digital image data from the memory unit 30 to the data interface unit 40, the input / output ports of the signals output 107 signals of the timing controller unit 50. Since the 107 input patterns of the pattern and the data interface unit 40 are required, a total of 214 excessive signal patterns are required, and the system itself becomes complicated and large.

According to the present invention, the timing controller unit 50 does not generate the 107 data shift signals f_107sft itself generated by the timing controller unit 3 of FIG. 1 and provided to the data interface unit 2. 40) is provided internally, and the timing controller unit 50 is characterized in that the data interface unit 40 provides only a reference signal and a clock necessary for generating the shift signal.

4 is a block diagram for explaining the above-described embodiment of the present invention. The reference signal generated by the timing controller unit 50 and the main clock corresponding to 50 MHz (or 2 MHz) are output using two specific ports of the timing controller unit 50, and the data interface unit 40 also specifies the reference signal. The reference signal and the main clock are input to two ports to generate a signal f_107sft for controlling input of one line data from the memory unit 30 using the reference signal.

Referring to FIGS. 2 and 3, a driving apparatus of the PDP-TV using the control signal generating apparatus will be described. That is, the analog composite video signal processor 100, the ADC unit 20, the memory unit 30, and the data interface unit 40 for processing the composite analog video signal input from the antenna by the AV unit 10. PDP comprising a digital data processing unit 200 for converting a video signal into digital data, a high voltage driving circuit unit 80, a holding / scanning driving IC 70, and an address driving IC 60 to perform PDP gradation processing. In the PDP-TV system composed of the driving unit 300, the amount of one line which is controlled by the signal processing of the entire system of the memory unit 30 and the data interface unit 40, and shifted from the memory unit 30. A timing controller unit (50) for providing a reference signal and a main clock to the data interface unit (40) so as to generate a signal for controlling the input and output of digital image data; The memory unit 30 of the digital data processing unit 200 receives a vertical / horizontal synchronization signal and a main clock as inputs, and generates a control clock for generating a write / read address clock and a logic control pulse required to drive the memory unit 30. A generator 600, a data rearranger 400 for rearranging digital image data, and an address generator 500 for generating a read / write address clock, and the write / output generated by the control clock generator 600. Outputs the selected data to the data interface unit 40 according to the control of the read address clock; The data interface unit 40 generates a signal for shifting one line of digital image data from the memory unit 30 by using the reference signal and the clock provided by the timing controller unit 50, and the memory unit. The digital image data inputted from (30) is made into a data stream form suitable for PDP gradation processing, and is output to the PDP driver (300).

As described above, in the present invention, 107 data shift signals f_107sft generated by the timing controller unit 3 of the PDP-TV system and used to shift the memory unit 1 from the memory unit 1 to the interface unit are provided. ) Is not made by the timing controller unit 50, but is made inside the data interface unit 40. In the timing controller unit 50, only the reference signal and the main clock necessary to make the shift signal are generated by the data interface unit 40. By providing the configuration provided, reducing the input / output pattern of the signal from 214 to 4 has the effect of simplifying the system design and improving the control complexity.

Claims (4)

Analog composite video signal processing unit 100 for processing composite analog video signal input from antenna by AV unit 10, ADC unit 20, memory unit 30, and data interface unit 40 And a digital data processor 200 for converting the image signal into digital data, a high voltage driver circuit 80, a sustain / scan driver IC 70, and an address driver IC 60 to perform PDP gray scale processing. In the PDP-TV system consisting of 300), The signal processing of the entire system of the memory unit 30 and the data interface unit 40 is controlled, and a signal for controlling the input / output of a line amount of digital image data shifted from the memory unit 30 is generated. A timing controller unit (50) for providing a reference signal and a main clock to the data interface unit (40) so as to enable the data signal; The memory unit 30 of the digital data processor 200 generates a logic control pulse required to drive a write / read address clock and a memory unit 30 by inputting a vertical / horizontal synchronization signal and a main clock. A clock generator 600, a data rearrangement unit 400 for rearranging digital image data, and an address generator 500 for generating a read / write address clock, and the write generated by the control clock generator 600. / Outputs the selected data to the data interface unit 40 according to the control of the read address clock; The data interface unit 40 generates a signal for shifting one line of digital image data from the memory unit 30 by using the reference signal and the clock provided by the timing controller unit 50, and the memory unit. And the digital image data inputted from (30) into a data stream form suitable for PDP gradation processing and outputted to the PDP driver (300). The apparatus of claim 1, wherein the digital image data shift signals generated by the data interface unit are 107 signals (f_107sft). The PDP-TV according to claim 1, wherein the reference signal and the main clock are inputted and outputted using two specific ports of the timing controller unit 50 and two specific ports of the data interface unit 40. Drive system. In the driving method of a PDP-TV having an analog composite signal processing unit 100, a digital data processing unit 200 and a PDP driving unit 300, A first process of converting an analog signal input from an antenna into digital image (R, G, B) data in the ADC unit 20 and outputting the digital signal to the digital data processing unit 200; Receives the above digital image data and reconstructs data of one field into a plurality of subfields for PDP gray level processing, and then rearranges the most significant bit from the least significant bit to the least significant bit, and resets the selected clock to the address generator's address clock. The data interface unit 40 outputs the data from the memory unit 30 using the reference signal and the main clock provided from the timing controller unit 50 to the data interface unit 40. A second process of generating 107 shift signals f_107 sft for shifting to 40; A third process of receiving digital image data from the memory unit 30 under the control of the 107 data shift signals f_107sft of the data interface unit 40 and providing the digital image data in the form of a digital stream to the PDP driver 300 is performed. A driving method of a PDP-TV using a shift signal of digital image data, characterized in that it comprises a.

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