JPH05175503A - Thin film transistor and manufacturing method thereof - Google Patents

Abstract

(57) [Summary] [Structure] The first semiconductor layer 4 serving as a channel is formed of the lower semiconductor layer 4a containing no nitrogen element and carbon element and the upper semiconductor layer 4b containing nitrogen element or carbon element, and at the same time, ohmic contact is formed. The second semiconductor layer 5 to be the contact layer is formed of a microcrystalline semiconductor layer. Further, the first semiconductor layer 4 serving as the channel layer is formed of the lower semiconductor layer 4a containing no nitrogen element or carbon element and the upper semiconductor layer 4b containing nitrogen element or carbon element, and the second semiconductor layer 4 serving as an ohmic contact layer. The semiconductor layer 5 is formed of a microcrystalline semiconductor, and a part of the microcrystalline semiconductor layer 5 is removed by etching to form a source / drain. [Effect] It is possible to provide a high-definition thin film transistor with excellent characteristics, the film formation process is simplified, and the ohmic contact layer 5 can be accurately etched without providing a special etching stopper layer. Therefore, the thin film transistor can be stably manufactured by a simple process even during mass production.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor and a method for manufacturing the same, and more particularly to a thin film transistor which can be suitably used for an active matrix type liquid crystal display device and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, as a thin film transistor used in an active matrix type liquid crystal display device or the like, a type in which a transparent conductive layer serving as a pixel electrode is located above the transistor and a type in which it is located below the transistor The manufacturing method and the structure of each thin film transistor are shown in FIGS.

FIG. 4 shows a type in which a transparent conductive layer which becomes a pixel electrode is located below a transistor.

First, as shown in FIG. 1A, a transparent conductive layer 22 to be a pixel electrode and a first conductive layer 23 to be a gate electrode are formed on an insulating substrate 21 made of glass or the like by a vacuum deposition method or a vacuum deposition method. It is formed by a sputtering method or the like, and this first conductive layer 23 is formed into a predetermined pattern by etching. Next, as shown in FIG. 3B, the transparent conductive layer 22 is formed into a predetermined pattern by etching. next,
As shown in FIG. 3C, the insulating layer 2 that will become the gate insulating film.
4, 25, a first semiconductor layer 26 to be a channel layer, and a silicon nitride layer 27 that acts as a stopper layer for etching are formed. The insulating layer 24 serving as a gate insulating film is made of, for example, a tantalum oxide layer, and the insulating layer 24 serving as a gate insulating film is made of a silicon nitride layer. The first semiconductor layer is composed of an i-type amorphous silicon layer or the like. Further, the silicon nitride layer 27 as the etching stopper layer contains a large amount of nitrogen element and has an energy band gap of 5.0 eV or more.
Next, as shown in FIG. 3D, patterning is performed so that the silicon nitride layer 27 as an etching stopper layer remains only on the gate electrode 23. Next, as shown in FIG. 7E, the second semiconductor layer 28 to be an ohmic contact layer is formed by, for example, the plasma CVD method. The second semiconductor layer 28 is made of, for example, an n ⁺ amorphous silicon layer. Next, as shown in FIG.
A contact hole 29 is formed on the side of the transistor. Next, as shown in FIG. 3G, second conductive layers 30 and 31 to be the source / drain electrodes are formed. In addition,
The second conductive layer 30 is made of molybdenum silicide or the like, and the second conductive layer 31 is made of aluminum or the like. Next, as shown in FIG. 3H, the second conductive layers 30 and 31 on the gate electrode 23 and the second semiconductor layer 28 are separated by etching to form a source and a drain. During this etching, the silicon nitride layer 27 serves as a stopper layer.

Finally, a passivation layer 32 made of a silicon nitride layer or the like is formed and completed.

As described above, in the thin film transistor used in the conventional active matrix type liquid crystal display device or the like, the second semiconductor layer 28 serving as the ohmic contact layer is provided on the first semiconductor layer 26 serving as the channel layer, and the second semiconductor layer 28 is provided. The central portion of the semiconductor layer is divided by, for example, etching by using a mixed solution of HNO ₃ (20) with respect to HF (1) in a volume ratio.
In order to prevent the first semiconductor layer 26 from being lost by over-etching when dividing into 8, and to prevent a part of the second semiconductor layer 28 from remaining to reduce the off resistance of the transistor, The stopper layer 27 is formed on the first semiconductor layer 26 so that a predetermined portion of the second semiconductor layer 28 is etched. That is, n
The second semiconductor layer 28 made of ⁺ -type amorphous silicon or the like can be easily etched only with the same etchant as the first semiconductor layer 26 made of i-type amorphous silicon or the like, and therefore serves as an etching stopper layer. The silicon nitride film 27 was required.

In the method of manufacturing the thin film transistor described above,
Since etching is performed in each step of FIGS. 4A, 4B, 4D, 4F, and 4H, five photomasks are required.

FIG. 5 shows a method of manufacturing a thin film transistor of the type in which the transparent conductive layer is located above the transistor.

First, as shown in FIG. 1A, a first conductive layer 52 to be a gate electrode is formed on an insulating substrate 51 and patterned. Next, as shown in FIG. 6B, the surface of the first conductive layer 52 is anodized to form the anodized layer 53.
To form. Next, as shown in FIG. 3C, an insulating layer 54 that will be a gate insulating film, a first semiconductor layer 55 that will be a channel layer, and a silicon nitride layer 56 that will function as an etching stopper layer will be formed. The silicon nitride layer as a stopper layer for this etching is also the same as the silicon nitride layer 27 shown in FIG. Next, as shown in FIG. 3D, the silicon nitride layer 5 is formed only on the gate electrode 53.
Most of the silicon nitride layer 56 is etched so that 6 remains. Next, as shown in FIG. 7E, the second semiconductor layer 57 to be an ohmic contact layer is formed. Next, as shown in FIG. 6F, the peripheral portions of the second semiconductor layer 57 and the first semiconductor layer 55 are removed by etching or the like. Next, as shown in FIG. 6G, a second conductive layer 58 to be the source / drain electrodes is formed and patterned. In this step, the transparent conductive layer 59 described later is used.
So that the first semiconductor layer 55 and the second semiconductor layer 57 do not come into contact with each other, the peripheral portions of the first semiconductor layer 55 and the second semiconductor layer 57 are completely covered with the second conductive layer 58. Pattern the second conductive layer 58 as described above. Next, as shown in FIG. 3H, a transparent conductive layer 59 to be a pixel electrode is formed and patterned. Finally, as shown in FIG. 1I, a passivation layer 60 made of a silicon nitride layer or the like is formed and completed.

In the method of manufacturing the active matrix substrate described above, a photomask is required in each step of FIGS. 5A, 5D, 5F, 5G and 5H, and at least five photomasks are required.

As described above, in the conventional thin film transistor, since the stopper layers 27 and 56 for etching which are unnecessary for the function of the transistor are formed, the channel length of the transistor becomes long and it is difficult to achieve high definition. There was a problem that there was. In addition, the etching stopper layer 2
In order to form Nos. 7 and 56, many photomasks are required, and there is a problem that the photoprocess takes time and mass productivity is poor. In particular, in a device in which a large number of such thin film transistors are formed, the manufacturing yield is significantly reduced due to the complexity of the manufacturing process, and therefore it is desired to simplify the manufacturing process as much as possible.

[0012]

The present invention has been made in view of the above problems of the prior art, and is characterized in that a first conductive layer to be a gate electrode on a substrate, An insulating layer to be a gate insulating film and a first semiconductor layer to be a channel layer are formed, and a second semiconductor layer to be an ohmic contact layer and a second semiconductor layer to be a source / drain electrode are formed on the first semiconductor layer. In the thin film transistor formed by dividing the conductive layer, the first semiconductor layer is formed of a lower semiconductor layer containing no nitrogen element and carbon element and an upper semiconductor layer containing nitrogen element or carbon element, and the second semiconductor layer is formed. The semiconductor layer is formed of a microcrystalline semiconductor layer.

Further, (a) a step of forming a first conductive layer to be a gate electrode on a predetermined portion of the substrate, and (b) an insulating layer to be a gate insulating film on the first conductive layer, A first semiconductor layer composed of a lower semiconductor layer containing no nitrogen element and a carbon element and an upper semiconductor layer containing a nitrogen element or a carbon element, a second semiconductor layer composed of a microcrystalline semiconductor layer, and a source / drain electrode A step of sequentially stacking a second conductive layer, and (c) a step of etching and removing the second conductive layer, the second semiconductor layer, and the first semiconductor layer on the upper peripheral portion of the first conductive layer , (D) a step of etching away the second conductive layer and the second semiconductor layer in the central portion on the first semiconductor layer.

[0014]

As described above, the upper layer of the first semiconductor layer to be the channel layer is formed of the semiconductor layer containing the nitrogen element or the carbon element, and the second semiconductor layer to be the ohmic contact layer is the microcrystalline semiconductor layer. If it is formed by, the first semiconductor layer and the second semiconductor layer can be continuously formed using the same apparatus, and etching between the semiconductor layer containing a nitrogen element or a carbon element and the microcrystalline semiconductor layer can be performed. A semiconductor layer containing nitrogen element or carbon element with selectivity can be used as an etching stopper, a special etching stopper layer becomes unnecessary, and the channel length of the transistor can be shortened to achieve high definition. At the same time, the photo process can be simplified, and a transistor with favorable characteristics can be formed.

[0015]

The present invention will be described in detail below with reference to the accompanying drawings. FIG. 1 is a diagram showing a manufacturing process of a thin film transistor according to the present invention, and 1 is an insulating substrate made of glass or the like.

First, as shown in FIG. 1A, a first conductive layer 2 to be a gate electrode is formed on a substrate 1 to a thickness of about 2000 Å by a vacuum deposition method or a sputtering method and patterned by an etching method or the like. To do. For this first conductive layer, chromium (Cr), tantalum (Ta), aluminum (Al), or the like is preferably used. Further, as an etching solution, an aqueous solution of cerium ammonium nitrate is preferably used for etching chromium, dry etching is used for etching tantalum, and phosphoric acid is preferably used for etching aluminum.

Next, as shown in FIG. 1B, the insulating layer 3 to be the gate insulating film, the lower semiconductor layer 4a containing no nitrogen element and carbon element and the nitrogen element or the nitrogen element are formed on the first conductive layer 2. A first semiconductor layer 4 including an upper semiconductor layer 4b containing a carbon element, a second semiconductor layer 5 including a microcrystalline semiconductor layer, and a second conductive layer 5 serving as a source / drain electrode are sequentially laminated.

The insulating layer 3 has a single layer structure of a silicon nitride layer, or a double layer structure of a silicon nitride layer and a tantalum oxide layer. The silicon nitride film is formed to a thickness of about 2000Å by, for example, a plasma CVD method, and the tantalum oxide film is formed to a thickness of about 2000Å by a sputtering method or an anodic oxidation method.

The first semiconductor layer 4 is composed of a lower semiconductor layer 4a containing no nitrogen element and carbon element and an upper semiconductor layer 4b containing nitrogen element or carbon element.
That is, the lower semiconductor layer 4a containing no nitrogen element and carbon element is a carrier gas and a silane gas (SiH ₄ )
The upper semiconductor layer 4b, which is formed to a thickness of about 200 Å by a plasma CVD method using, and which contains a nitrogen element or a carbon element, has a carrier gas and a silane gas (SiH ₄ ) in which ammonia gas (NH ₃ ) or methane gas (CH ₄ ) is added. Is formed to a thickness of about 800 Å by a plasma CVD method in which is mixed. The upper semiconductor layer 4b is formed so as to have etching selectivity with an ohmic contact layer 5 which will be described later, and to have a function as an etching stopper layer. The etching rate for ohmic contact layer 5>
A semiconductor layer may be formed to serve as the upper semiconductor layer 4b. The upper semiconductor layer 4b has an energy band gap of 5.0 eV or less, preferably 2.5 eV or less, and a dark conductivity of 5 × 10 ^-12 Ω ^-1 cm ^-1 or more 1 × 10 ^-9 Ω ^-1.・
It is preferable to add a nitrogen element or a carbon element so as to be less than or equal to cm ^{−1 because} the off resistance and the on current of the transistor become equivalent to those of the conventional product. The content of this nitrogen element or carbon element is controlled by the flow rate ratio of methane gas (CH ₄ ) or ammonia gas (NH ₃ ).

In FIG. 2, a nitrogen element or a carbon element of a thin film transistor in which an upper semiconductor layer 4b having a thickness of 800Å containing a nitrogen element or a carbon element is formed on a lower semiconductor layer 4a having a thickness of 50Å containing no nitrogen element or a carbon element. 3 shows the relationship between the content of P and the on-current of the transistor. Figure 2
The middle circles indicate the case where the upper semiconductor layer 4b contains a nitrogen element, and the white circles indicate the case where the upper semiconductor layer 4b contains the carbon element. The horizontal axis of FIG. 2 shows the flow rate ratio of the ammonia gas to the silane gas and the flow rate ratio of the methane gas to the silane gas. As is apparent from FIG. 2, when the flow rate ratio of ammonia gas to silane gas is 0.01, the on-current of the transistor is 1.5 × 10 ⁻⁶ A,
Further, the flow rate ratio of ammonia gas to silane gas is 0.
When it is 1, the on-current of the transistor is 1 × 10 ⁻⁷ A. Therefore, when the upper semiconductor layer 4b contains a nitrogen element, the upper semiconductor layer 4b is formed by setting the flow rate ratio of the ammonia gas to the silane gas to 0.1 or less.
It is desirable to form it so as to contain 20 atomic% or less of nitrogen element. When the flow ratio of methane gas to silane gas is 0.1, the on-current of the transistor is 1.7 × 10 ⁻⁶ A, and even when the flow ratio of methane gas to silane gas is 2.0, the transistor is on. The current is 1 × 10 ⁻⁶ A. Therefore, even if the flow rate ratio of methane gas to silane gas is 2.0 or more, there is no problem in the characteristics of the transistor. However, if the flow rate ratio of methane gas to silane gas is 10 or more, it is difficult to etch such a semiconductor layer. It is preferable that the flow rate ratio of methane gas to silane gas is set to 10 or less, and the upper semiconductor layer 4b is formed to contain 40 atomic% or less of carbon element.

The second semiconductor layer 5 serving as the ohmic contact layer shown in FIG. 1B is formed of, for example, phosphine (PH).
₃ ) etc. in high concentration (converted to phosphorus element, 10 ¹⁸ to 10 ²¹
(/ Piece / cm ³ ) contained in the n ⁺ type microcrystalline semiconductor layer. The n ⁺ type microcrystalline semiconductor layer 5 is also formed by the plasma CVD method or the like similarly to the first semiconductor layer 4 described above. However, compared with the first semiconductor layer 4, the flow rate ratio of silane gas is reduced and plasma is formed. It is formed by increasing the power of the high frequency power source of the CVD apparatus. When formed in this manner, crystalline silicon having a grain size of about 100Å is scattered and deposited in the amorphous silicon layer, and the dark conductivity is 1 × 10 ⁰ Ω ^-1 cm ^-1.
That is all. That is, in the present invention, the n ⁺ type microcrystalline semiconductor layer is defined to have a dark conductivity of 1 × 10 ⁰ Ω ^-1 cm ^-1 or more. This second semiconductor layer 5 has a thickness of 1
It is formed to about 000Å. This second semiconductor layer 5 is
Since the first semiconductor layer 4 can be formed by the plasma CVD apparatus like the first semiconductor layer 4, it may be formed in-line by using the same apparatus. In the thin film transistor according to the present invention, the first semiconductor layer 4 that serves as a channel layer is composed of the lower semiconductor layer 4a containing no nitrogen element and carbon element and the upper semiconductor layer 4b containing nitrogen element or carbon element. Therefore, the second semiconductor layer 5 serving as the ohmic contact layer comes into contact only with the upper semiconductor layer 4b containing the nitrogen element or the carbon element of the first semiconductor layer 4 serving as the channel layer.

The second conductive layer 6 is formed of aluminum, tantalum, chromium, titanium (Ti) or the like, and has a thickness of 1000 to 400 by a sputtering method or a vacuum deposition method.
It is formed to about 0Å. Note that, for example, molybdenum silicide (MoSi ₂ ) or the like is provided between the second conductive layer 6 and the above-mentioned second semiconductor layer 5 so that the second conductive layer 6 is included in the second semiconductor layer 5. It may be possible to prevent the diffusion.

Next, as shown in FIG. 3C, the above-mentioned second conductive layer 6, second semiconductor layer 5, and first semiconductor layer 4 are left on the gate electrode 2 and its peripheral portion. So that it is removed by etching. When the second conductive layer 6 is also etched, the etching liquid as described above is used. Further, in this step, when etching the second semiconductor layer 5 and the first semiconductor layer 4, the volume ratio of HF (3): HNO is set.
₃ The etching solution of (1) is used. In this way, the second semiconductor layer 5 and the first semiconductor layer 4 can be etched by using the etching solution of HF (3): HNO ₃ (1) in a volume ratio. When the second conductive layer 6, the second semiconductor layer 5, and the first semiconductor layer 4 are etched, the same photomask is used.

Next, as shown in FIG. 3D, a transparent conductive layer 7 made of tin oxide or the like is formed to a thickness of about 1000 Å by a sputtering method or the like. When the transparent conductive layer 7 is formed of tin oxide as described above, there is almost no change in the contact resistance with the n ⁺ type microcrystalline silicon layer 5 with time, and thus it is not necessary to specially pattern the source / drain electrodes as in the conventional case. ..

Finally, as shown in FIG. 6 (e), in order to divide the second semiconductor layer 5 to be the ohmic contact layer and the second conductive layer 6 to be the source / drain electrodes, these layers are transparent. The central portion of the conductive layer 7 on the gate electrode 2 is removed by etching. The transparent conductive layer 7 is, for example, a salt nitric acid-based etching solution using zinc as a catalyst, the second conductive layer 6 is the above-described etching solution, and the second semiconductor layer 5 is HF (1): HNO in a volume ratio. ₃ (17): An etching solution containing H ₂ O (17) may be used. Since this etching solution has no reactivity with the first semiconductor layer 4 made of the i-type amorphous silicon layer, the upper semiconductor layer 4b of the first semiconductor layer 4 must contain a nitrogen element or a carbon element. Together with this, it is possible to stably divide the second semiconductor layer 5 without providing a stopper layer for etching. Further, when the second semiconductor layer 5 is divided without providing a stopper layer for etching, the channel length L of the transistor is shortened, the on-current of the transistor is improved, and the channel width W can be reduced, so that high definition can be achieved. ..

Note that a passivation film made of a silicon nitride film or the like may be formed to protect the transistor.

[0027]

[Experimental Example] A thin film transistor was formed under the following conditions,
The relationship between the gate voltage and the drain current was investigated.

Substrate : Gate electrode : Material Chromium (Cr) manufacturing method Sputtering film thickness 1000Å Gate insulating film : Material silicon nitride film one-layer manufacturing method Plasma CVD method 1 torr power 0.8 W / cm ² Substrate temperature 400 ° C. 100% silane gas 16 cc / mit, ammonia gas 61 cc / mit, hydrogen gas 100 cc / mit, nitrogen gas 100 cc / mit Film thickness 4700 Å Lower semiconductor layer : Material i-type amorphous silicon manufacturing method Plasma CVD method 2 torr power 0.08 W / cm ² Substrate temperature 240 ° C. 100% silane gas 20 cc / mit, hydrogen gas 18
0 cc / mit film thickness 200 Å Upper semiconductor layer : material i-type amorphous silicon manufacturing method plasma CVD method 1 torr power 0.08 W / cm ² substrate temperature 240 ° C. 100% silane gas 200 cc / mit, ammonia gas 20 cc / mit film thickness 800 Å Microcrystalline semiconductor layer : Material n ⁺ type amorphous silicon manufacturing method Plasma CVD method 2 torr power 0.53 W / cm ² Substrate temperature 240 ° C. 100% silane gas 2 cc / mit, hydrogen gas 138
Hydrogen gas diluted to 500 ppm of cc / mit and phosphine 80 cc / mit Film thickness 1000Å Source / drain electrode : Material Double layer structure of molybdenum silicide layer and aluminum layer Sputtering film thickness Molybdenum silicide layer: 1000Å Aluminum layer: 3000Å A thin film transistor was formed under the above conditions and the relationship between the gate voltage and the drain current was examined. The result is shown in FIG. The source voltage Vd is 15 v, and the ratio of the channel width W to the channel length L is W / L = 5.4. As is clear from FIG. 2, when the gate voltage is 0 to 1 volt, the drain current drops to 2 × 10 ⁻¹⁴ A, and when the gate voltage is 15 V, the drain current is 10 V.
^-It increased to ^-6 A, and it can be seen that the off resistance and the on current are both satisfactory for the transistor of the active matrix type liquid crystal display device.

Since the semiconductor layer containing the carbon element also has a dark conductivity similar to that of the semiconductor layer containing the nitrogen element, instead of the semiconductor layer containing the nitrogen element described above,
A thin film transistor having similar characteristics can be obtained by using a semiconductor layer containing a carbon element.

[0030]

As described above, according to the thin film transistor of the present invention, the first semiconductor layer serving as the channel layer is the lower semiconductor layer containing no nitrogen element and carbon element and the upper semiconductor layer containing nitrogen element or carbon element. Since the second semiconductor layer to be an ohmic contact layer is formed of a microcrystalline semiconductor layer while being formed of a semiconductor layer, a thin film transistor with high definition and favorable characteristics can be provided.

According to the method of manufacturing a thin film transistor according to the present invention, the first semiconductor layer serving as the channel layer is the lower semiconductor layer containing no nitrogen element and carbon element and the upper semiconductor layer containing nitrogen element or carbon element. The second semiconductor layer to be an ohmic contact layer is formed of a microcrystalline semiconductor layer and the source / drain is formed by etching away a part of the microcrystalline semiconductor layer. In addition, the ohmic contact layer can be accurately etched without providing a special etching stopper layer, and a thin film transistor can be stably manufactured in a simple process even during mass production.

[Brief description of drawings]

1A to 1E are views showing a manufacturing process of a thin film transistor according to the present invention.

FIG. 2 is a diagram showing the relationship between the contents of nitrogen element and carbon element in the upper semiconductor layer and the on-current of the transistor.

FIG. 3 is a diagram showing a relationship between a gate voltage and a drain current of a thin film transistor according to the present invention.

FIGS. 4A to 4H are diagrams showing a conventional method for manufacturing a thin film transistor.

5A to 5I are views showing another conventional method for manufacturing a thin film transistor.

[Explanation of symbols]

1 ... Substrate, 2 ... First conductive layer, 3 ... Insulating layer, 4 ... First semiconductor layer, 4a ... Lower semiconductor layer containing no nitrogen element and carbon element, 4b ... Upper semiconductor layer containing nitrogen element or carbon element, 5 ...
Second semiconductor layer, 6 ... Second conductive layer.

Claims (4)

[Claims] 1. A first conductive layer to be a gate electrode, an insulating layer to be a gate insulating film, and a first semiconductor layer to be a channel layer are formed on a substrate, and an ohmic contact is formed on the first semiconductor layer. In a thin film transistor formed by dividing a second semiconductor layer to be a contact layer and a second conductive layer to be a source / drain electrode, the first semiconductor layer is a lower semiconductor layer containing no nitrogen element and carbon element and nitrogen. A thin film transistor, which is formed of an upper semiconductor layer containing an element or a carbon element, and the second semiconductor layer is formed of a microcrystalline semiconductor layer. 2. The thin film transistor according to claim 1, wherein the upper semiconductor layer contains up to 20 atomic% of nitrogen element. 3. The thin film transistor according to claim 2, wherein the upper semiconductor layer contains up to 40 atomic% of carbon element. 4. A step of: (a) forming a first conductive layer to be a gate electrode on a predetermined portion of the substrate; and (b) an insulating layer to be a gate insulating film on the first conductive layer. A first semiconductor layer composed of a lower semiconductor layer containing no nitrogen element and a carbon element and an upper semiconductor layer containing a nitrogen element or a carbon element, a second semiconductor layer composed of a microcrystalline semiconductor layer, and a source / drain electrode A step of sequentially stacking a second conductive layer, and (c) a step of etching and removing the second conductive layer, the second semiconductor layer, and the first semiconductor layer on the upper peripheral portion of the first conductive layer , (D) A method of manufacturing a thin film transistor, which comprises the step of etching away the second conductive layer and the second semiconductor layer in the central portion on the first conductive layer.