JP2513664B2 - Method for manufacturing thin film transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention relates to a method of manufacturing a staggered amorphous silicon thin film transistor, in which a source / drain electrode is formed of n ⁺ a in the process of forming an active layer of amorphous Si on the source / drain electrode. In order to prevent the natural oxide film from being formed on the -Si surface and deteriorating the contact characteristics, the film is formed while increasing the growth temperature of a-Si, which becomes the active layer, from a low temperature to a high temperature. .

[Industrial applications]

The present invention relates to a method of manufacturing a thin film transistor having an active layer formed of a staggered amorphous silicon layer,
In particular, the present invention relates to a method for forming an active layer and a gate insulating film laminated thereon.

[Conventional technology]

As a switching element of an active matrix type liquid crystal panel, an active layer is made of amorphous silicon (a-Si).
Although thin film transistors (TFTs) that are formed of layers and have an inverted staggered type electrode structure were often used, the staggered type structure was reconsidered and the device characteristics improved because the manufacturing process of the liquid crystal display matrix could be simplified. And various stabilizations have been studied.

The conventional staggered TFT manufacturing method is shown in FIG.
The manufacturing steps will be described in order.

As shown in FIG. 1A, a metal film 2 to be source / drain electrodes is formed on an insulating substrate, for example, a glass substrate 1.
And the n ⁺ a-Si layer 3 is laminated on it, and the source,
A resist film 7 for patterning the drain electrode is formed [see FIG.

Next, using the resist film 7 as a mask, the n ⁺ a-Si layer 3 is formed.
And the metal film 2 are sequentially etched, and then the resist film 7 is formed.
Are removed [see (b) in the figure].

Then, the n ⁺ a-Si layer 3 is subjected to a surface treatment with a hydrofluoric acid-based etchant to remove the natural oxide film on the surface [FIG.
reference〕.

Then, the a-Si: H layer 4 which becomes the active layer and the gate insulating film becomes
A SiN (silicon nitride) layer 5 is formed [see FIG. As the gate insulating film, silicon dioxide (Si
An O ₂ ) layer or the like may be used.

Then, a conductive layer 6 to be a gate electrode is formed, and a resist film 8 for patterning the gate electrode is formed thereon (see FIG. 8E).

Then, using the resist film 8 as a mask, the conductive layer 6, Si
After the N layer 5, a-Si: H layer 4, and n ⁺ a-Si layer 3 are sequentially etched, the resist film 8 used as a mask is removed [see FIG.

Although an example in which the conductive layer 6 and the a-Si: H layer 4 are patterned by a single photolithography process is shown here,
Of course, these may be etched in separate steps.

 The staggered TFT is completed by the above.

[Problems to be solved by the invention]

In the above conventional TFT manufacturing method, the temperature of the substrate is 200 ° C to
Plasma chemical vapor deposition (P-CVD) is performed at 300 ° C. to grow the a-Si: H layer 4. In this method, n ⁺ a−S
The oxygen (O ₂ ) adsorbed or remaining on the surface of the i-layer 3 in a trace amount or the oxygen decomposed by water (H ₂ O) causes n
^{+ The} surface of the a-Si layer 3 is easily oxidized to form a thin oxide film. Therefore, the contact between the n ⁺ a-Si layer 3 and the a-Si: H layer 4 becomes insufficient, and it is difficult to stably obtain good characteristics.

It is an object of the present invention to provide a method for manufacturing a thin film transistor, in which an oxide film is not formed on the surface of a contact layer and good contact characteristics can be stably obtained.

[Means for solving problems]

In the present invention, when the a-Si: H layer 4 is grown on the n ⁺ a-Si layer 3, the film growth is started at a temperature not lower than the lowest temperature at which the film is initially deposited, and gradually increased. Temperature rises to a-
By the time the growth of the Si: H layer 4 ends and the growth of the next SiN layer 5 begins, a temperature at which good interface characteristics between the a-Si: H layer 4 and the SiN layer 5 are obtained, that is, 200 ° C to Keep the temperature at 300 ° C.

[Work]

Since the substrate temperature is low at the initial stage of the film growth of the a-Si: H layer 4, the surface of the n ⁺ a-Si layer 3 is suppressed from being oxidized, so that the contact characteristics are prevented from being deteriorated. −Si: H
In the vicinity of the interface between the layer 4 and the SiN layer 5, the temperature is raised to the usual film formation temperature (200 ° C to 300 ° C) of the a-Si: H layer 4, so the interface characteristics of both are the same as before, Good FET characteristics can be obtained.

〔Example〕

Conventionally, the substrate temperature was stabilized at a predetermined value in a vacuum, and then the film was formed at a constant temperature.
The film is formed while raising the temperature from about 0 ° C to about 250 ° C.

An embodiment of the present invention will be described below in the order of manufacturing steps thereof with reference to FIGS. 1 (a) to 1 (c).

7A and 7B are diagrams showing a film forming process of the a-Si: H layer 4 and the SiN layer 5, and correspond to the processes of FIGS. 2C and 2D. Further, FIG. 6C shows a pattern in which the substrate temperature is gradually raised during film formation.

The metal film 2, n ⁺ a-Si layer 3 is laminated on the glass substrate 1,
After patterning this, the surface of the n + a-Si layer 3 is slightly etched with a hydrofluoric acid-based etchant to remove the oxide film (SiO ₂ ) formed on the surface [First
See FIG. (A)].

Then, an a-Si: H layer is formed on the layer by plasma chemical vapor deposition (P-CVD), and then silicon nitride (SiN) is formed on the layer.
Although the layer is grown, in this embodiment, after the substrate is placed in the reaction chamber, the reaction chamber is cooled sufficiently so as not to be exposed to a high temperature such that the surface of the n ⁺ a-Si layer 3 is oxidized.

After the substrate is placed in the reaction chamber and the degree of vacuum reaches a predetermined value, the substrate temperature is raised to exceed the minimum temperature at which the a-Si: H layer grows. Start to grow. After that, as shown in FIG. 7C, the a-Si: H layer 4 is formed while gradually raising the substrate temperature, and a-S
Until the film formation of the i: H layer 4 is completed and the film formation of the next SiN layer 5 is started, the normal a-Si: H layer 4 film formation temperature, that is, 200 to 300 ° C.
(In this example, about 260 ° C.). a-Si: H
After the thickness of the layer 4 reaches a predetermined value, the SiN layer 5 is grown,
The laminated body shown in FIG. This corresponds to FIG. 2 (d), and there is no structural change.
However, in the present embodiment, since the oxide film is not formed on the surface of the n ⁺ a-Si layer 3, the contact between the oxide film and the a-Si: H layer 4 is good, which is different from the conventional case.

The subsequent manufacturing process may be carried out in the same manner as in the conventional case, and in the present embodiment, as shown in FIG. 2 (f).
TFT is obtained.

As described above, the TFT obtained in this example has good contact between the contact layer n ⁺ a: Si layer 3 and the active layer composed of the a-Si: H layer 4 and reproduces it sufficiently. And TFT characteristics are stable.

〔The invention's effect〕

As described above, according to the present invention, the surface of the n ⁺ a-Si layer 3 which is the contact layer constituting the source / drain electrodes is prevented from being oxidized at the initial stage of the film formation process of the a-Si: H layer 4. As a result, the contact characteristics of the source / drain electrodes become stable, and the TFT characteristics, especially the on-current value, become stable.

Therefore, it becomes easy to use the staggered a-Si TFT in the liquid crystal panel, which can simplify the active matrix manufacturing process.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of an embodiment of the present invention, and FIG. 2 is an explanatory diagram of a conventional TFT. In the figure, 1 is an insulating substrate (glass substrate), 2 is a metal film, 3 is a contact layer (n ⁺ a-Si layer), and 4 is an active layer (a).
-Si: H layer), 5 indicates a gate insulating film (SiN layer).

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Koichi Tachioka 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Fujitsu Limited Fujitsu Limited (72) Teruhiko Ichimura 1015, Kamedotachu, Nakahara-ku, Kawasaki City, Fujitsu Limited

Claims (1)

(57) [Claims] 1. A source electrode and a drain electrode having a contact layer composed of a metal film and an n ⁺ a-Si layer laminated on the insulating substrate, an active layer composed of an a-Si: H layer, and a gate. A method for manufacturing a staggered amorphous silicon thin film transistor having a structure in which an insulating film and a gate electrode are sequentially stacked, wherein an active layer of a-Si: H is formed on the n ⁺ a-Si contact layer by plasma enhanced chemical vapor deposition. When the gate insulating film and the gate insulating film are continuously formed, the substrate temperature is set to a in a vacuum chamber under a predetermined vacuum degree.
− Raise from a temperature lower than the lowest temperature at which Si: H is deposited,
After the temperature exceeds the minimum temperature, the a-Si: H layer is grown while raising the temperature, and the interface characteristics with the gate insulating film on the a-Si: H layer are improved before the a-Si: H layer reaches a predetermined thickness. A method for manufacturing a thin film transistor, comprising: reaching a temperature for normalizing and then growing the gate insulating film.