JPH0444256A - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPH0444256A JPH0444256A JP2149544A JP14954490A JPH0444256A JP H0444256 A JPH0444256 A JP H0444256A JP 2149544 A JP2149544 A JP 2149544A JP 14954490 A JP14954490 A JP 14954490A JP H0444256 A JPH0444256 A JP H0444256A
- Authority
- JP
- Japan
- Prior art keywords
- multilayer film
- substrate
- semiconductor chip
- cap
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 28
- 239000000758 substrate Substances 0.000 claims description 15
- 238000001816 cooling Methods 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 7
- 230000017525 heat dissipation Effects 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- 239000004642 Polyimide Substances 0.000 claims description 4
- 239000010949 copper Substances 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 229920001721 polyimide Polymers 0.000 claims description 4
- 239000011810 insulating material Substances 0.000 claims 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 7
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 7
- 238000004806 packaging method and process Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000008054 signal transmission Effects 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 239000004519 grease Substances 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 210000002784 stomach Anatomy 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の実装技術、特に、マルチチップ化
によって高密度実装を行うために用いて効果のある技術
に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a mounting technology for semiconductor devices, and in particular to a technology that is effective when used to perform high-density mounting through multi-chip technology.
大型コンピュータなどに用いる半導体装置では、パッケ
ージに窒化アルミ （ＡＩＮ）基板を用いている。例え
ば、「日経マイクロデバイス」１９８９年６月号（５０
〜５１頁）に記載のように、ＡＩＮを用いたピングリッ
ドアレイ （ＰＧＡ）上にポリイミドを絶縁層とする多
層配線層を形成し、この配線層上にＬＳＩチップを搭載
し、さらにＬＳＩチップにＡＩＮキャップをはんだ付け
する構成がとられている。Semiconductor devices used in large-scale computers use aluminum nitride (AIN) substrates for their packages. For example, "Nikkei Microdevice" June 1989 issue (50
51), a multilayer wiring layer with polyimide as an insulating layer is formed on a pin grid array (PGA) using AIN, an LSI chip is mounted on this wiring layer, and the LSI chip is further mounted on the wiring layer. A configuration is adopted in which the AIN cap is soldered.
ところが、前記の如＜ＡＩＮ基板を用いた従来の実装構
造においては、ＣＣＢ （Ｃｏｎｔｒｏｌｌｅｄ Ｃｏ
ｔｌａｐｓｅ Ｂｏｎｄｉｎｇ）接続にし、かつ同一基
板上に複数の半導体チップを搭載してマルチチップ化を
行右うとした場合、大規模化による電気的遅延に対する
配慮がなされていなかった。However, in the conventional mounting structure using the AIN board as described above, CCB (Controlled Co., Ltd.
In the case of trying to create a multi-chip structure by using a lapse bonding (trapse bonding) connection and mounting a plurality of semiconductor chips on the same substrate, no consideration was given to the electrical delay caused by the increase in scale.
また、５ｉ−ｏｎ−３ｉ構造にした場合、シリコン基板
にスルーホールを形成することができず、端子を周辺に
しか確保できないため、高密度実装化の障害になってい
る。Further, in the case of a 5i-on-3i structure, through holes cannot be formed in the silicon substrate and terminals can only be secured at the periphery, which is an obstacle to high-density packaging.
そこで、本発明の目的は、伝送特性を債なうことなくマ
ルチチップ化及びＣＣＢ接続による実装を行うことので
きる技術を提供することにある。Therefore, an object of the present invention is to provide a technology that allows multi-chip implementation and CCB connection implementation without compromising transmission characteristics.
本発明の前記目的と新規な特徴は、本明細書の記述及び
添付図面から明らかになるであろう。The above objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本戦において開示される発明のうち、代表的なものの概
要を簡単に説明すれば、以下の通りである。A brief overview of typical inventions disclosed in this competition is as follows.
すなわち、基板の一面にリードピンが立設されると共に
内部にスルーホールを有した基板と、前記スルーホール
に接続されると共に前記基板の他面に設けられる多層膜
と、バンプ電極を介して前記多層膜に搭載される少なく
とも１つの単導体チップと、該半導体チップの放熱面に
はんだ接合されるキャップとを設ける構成にしている。That is, a substrate with lead pins erected on one surface of the substrate and a through hole inside, a multilayer film connected to the through hole and provided on the other surface of the substrate, and a multilayer film connected to the through hole and provided on the other surface of the substrate, and a multilayer film connected to the through hole and provided on the other surface of the substrate, and The structure includes at least one single conductor chip mounted on the membrane and a cap soldered to the heat dissipation surface of the semiconductor chip.
上記した手段によれば、基板に加工性に優れる材料を用
いてスルーホールを設け、その誘電率の影響を避けるた
ｔに例えば低誘電率のポリイミドと導電性に優れる銅を
用いた多層膜を基板上に設け、この多層膜に信号伝送速
度が問題にされる半導体チップをＣＣＢ接続によって搭
載する。これにより、信号遅延を生じることなく高密度
実装を達成することができ、かつ、放熱特性を損なうこ
ともない。According to the above-mentioned method, a through hole is formed in the substrate using a material with excellent workability, and a multilayer film made of, for example, polyimide with a low dielectric constant and copper with excellent conductivity is formed on the t to avoid the influence of the dielectric constant. This multilayer film is provided on a substrate, and a semiconductor chip whose signal transmission speed is an issue is mounted on this multilayer film by CCB connection. As a result, high-density packaging can be achieved without causing signal delay, and heat dissipation characteristics are not impaired.
第１図は本発明による半導体装置の一実施例を示す断面
図である。FIG. 1 is a sectional view showing an embodiment of a semiconductor device according to the present invention.
ＡＩＮ材を用いた低熱膨張の基板１は、下部の全面に多
数の微細な径のリードピン２が立設され、さらに上面に
はリードピン２に連通ずるスルーホール１ａを介して接
続される配線層３ （多層膜）が形成されている。この
配線層３は、低誘電率のポリイミドを絶縁膜とし、銅を
配線材にして構成し、信号の伝送スピードの低下を防止
している。A low thermal expansion substrate 1 made of AIN material has a large number of fine-diameter lead pins 2 erected on the entire lower surface, and a wiring layer 3 connected to the lead pins 2 through through holes 1a on the upper surface. (multilayer film) is formed. This wiring layer 3 is constructed using polyimide with a low dielectric constant as an insulating film and copper as a wiring material to prevent a reduction in signal transmission speed.
配線層３上には、バンプ電極（ＣＣＢはんだ）４を接続
部にした複数の半導体チップ５が搭載されている。半導
体チップ５の各々の上面（放熱面）には、はんだ接合に
よるキャップ６が配設されている。このキャップ６は、
基板１の上面の４隅に立設したＡＩＮ材による支柱７に
よって支持され、この支柱７の両端がはんだ８によって
接合されている。A plurality of semiconductor chips 5 are mounted on the wiring layer 3 and have bump electrodes (CCB solder) 4 as connection parts. A cap 6 is provided on the upper surface (heat radiation surface) of each semiconductor chip 5 by soldering. This cap 6 is
The substrate 1 is supported by pillars 7 made of AIN material that are erected at the four corners of the upper surface, and both ends of the pillars 7 are joined by solder 8.
キャップ６０表面には、熱伝導グリース１１を介して強
制冷却手段としての水冷部１０を備えた水冷管９が密着
配設され、キャップ６から伝達される熱に対する熱交換
を行い、半導体チップ５の冷却を行っている。A water cooling pipe 9 equipped with a water cooling section 10 as a forced cooling means is closely disposed on the surface of the cap 60 via thermal conductive grease 11, and performs heat exchange with the heat transferred from the cap 6, thereby cooling the semiconductor chip 5. Cooling is in progress.
なお、配線層３上には、半導体チップ５のほか、ワイヤ
ボンディングによって配線層３に電気的に接続される半
導体チップ１２を搭載することもできる。また、図示を
省略しているが、ＴＡＢ（Ｔａｐｅ Ａｕｔｏｍａｔｅ
ｄ Ｂｏｎｄｉｎｇ） ！ｌ続による半導体チップを搭
載することもできる。In addition to the semiconductor chip 5, a semiconductor chip 12 electrically connected to the wiring layer 3 by wire bonding can also be mounted on the wiring layer 3. Although not shown, TAB (Tape Automate)
d Bonding)! It is also possible to mount a semiconductor chip in series.
以上の構成により、低ｆＩ！電率の配線層３は配線の浮
遊容量を少なくし、銅による配線材は配線抵抗を小さく
するように機能するので、信号遅延の要素を小さくする
ことができる。さらに、配線層３と半導体チップ５の接
続をバンプ電極４を介して行うことにより、ワイヤボン
ディングなどに比べて配線距離を短くするすることがで
きる。With the above configuration, low fI! The conductive wiring layer 3 functions to reduce the stray capacitance of the wiring, and the copper wiring material functions to reduce the wiring resistance, so that the signal delay factor can be reduced. Furthermore, by connecting the wiring layer 3 and the semiconductor chip 5 via the bump electrodes 4, the wiring distance can be shortened compared to wire bonding or the like.
したがって、リードピン２と半導体チップ５間の配線を
最短距離にし、遅延を最小にして信号伝送を行うことが
できるので、高密度実装を図っても信号遅延を生じさせ
ることがない。Therefore, it is possible to minimize the wiring distance between the lead pins 2 and the semiconductor chip 5 and to perform signal transmission with minimal delay, so that no signal delay occurs even when high-density packaging is attempted.
一方、放熱に関しては、半導体チップ５の放熱面にキャ
ップ６が接合され、さらには水冷管９がキャップ６に密
着して熱交換を行っているため、マルチチップ化を行い
ながら十分な放熱特性を得ることができる。On the other hand, regarding heat dissipation, the cap 6 is bonded to the heat dissipation surface of the semiconductor chip 5, and the water cooling tube 9 is in close contact with the cap 6 for heat exchange. Obtainable.
なお、配線層３には、配線材のほか、回路を構成するコ
ンデンサや抵抗器などの電子部品を内蔵させることもで
きる。In addition to wiring materials, the wiring layer 3 can also incorporate electronic components such as capacitors and resistors that constitute a circuit.
さらに、水冷管９は、ベローズ付き水冷ジャケットのほ
か、ペルチェ素子を利用した冷却スタッドに代えること
もできる。Furthermore, the water cooling pipe 9 can be replaced with a cooling stud using a Peltier element, in addition to a water cooling jacket with a bellows.
以上、本発明者によってなされた発明を実施例に基づき
具体的に説明したが、本発明は前記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることは言うまでもない。Above, the invention made by the present inventor has been specifically explained based on Examples, but it goes without saying that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. stomach.
例えば、接続部のボイドの発生を低減するため、キャッ
プ６０半導体チップ５側の面に凹凸を設けるようにして
もよい。For example, in order to reduce the occurrence of voids at the connection portion, irregularities may be provided on the surface of the cap 60 on the semiconductor chip 5 side.
本願において開示される発明のうち、代表的なものによ
って得られる効果を簡単に説明すれば、下記の通りであ
る。Among the inventions disclosed in this application, the effects obtained by typical ones are as follows.
すなわち、基板の一面にリードビンが立設されると共に
内部にスルーホールを存した基板と、前記スルーホール
に接続されると共に前記基板の他面に設けられる多層膜
と、バンプ電極を介して前記多層膜に搭載される少なく
とも１つの半導体チップと、該半導体チップの放熱面に
はんだ接合されるキャップとを設けるようにしたので、
高速性を確保しながら高密度実装及び高放熱特性の半導
体装置を得ることが可能になる。That is, a board with lead bins erected on one surface of the board and a through hole inside, a multilayer film connected to the through hole and provided on the other surface of the board, and a multilayer film connected to the through hole and provided on the other surface of the board, and the multilayer film connected to the through hole and provided on the other surface of the board, and the multilayer film connected to the through hole and provided on the other surface of the board. Since at least one semiconductor chip is mounted on the membrane and a cap is soldered to the heat radiation surface of the semiconductor chip,
It becomes possible to obtain a semiconductor device with high density packaging and high heat dissipation characteristics while ensuring high speed performance.
第１図は本発明による半導体装置の一実施例を示す断面
図である。
１・・・基板、１ａ・・・スルーホール、２・・・リー
ドピン、３・・・配線層、４・・・バンプ電極、５．１
２・・・半導体チップ、６・・・キャップ、７・・・支
柱、８・・・はんだ、９・・・水冷管、１０・・・水冷
部、１１・・・熱伝導グリース。
代理人 弁理士 筒 井 大 和FIG. 1 is a sectional view showing an embodiment of a semiconductor device according to the present invention. DESCRIPTION OF SYMBOLS 1... Substrate, 1a... Through hole, 2... Lead pin, 3... Wiring layer, 4... Bump electrode, 5.1
2... Semiconductor chip, 6... Cap, 7... Strut, 8... Solder, 9... Water cooling tube, 10... Water cooling section, 11... Thermal conductive grease. Agent Patent Attorney Daiwa Tsutsui
Claims (1)
スルーホールを有した基板と、前記スルーホールに接続
されると共に前記基板の他面に設けられる多層膜と、バ
ンプ電極を介して前記多層膜に搭載される少なくとも１
つの半導体チップと、該半導体チップの放熱面にはんだ
接合されるキャップとを具備することを特徴とする半導
体装置。 ２、前記多層膜は、絶縁材にポリイミドを用い、配線材
に銅を用いることを特徴とする請求項１記載の半導体装
置。 ３、前記多層膜に電子部品を内蔵させることを特徴とす
る請求項１記載の半導体装置。 ４、前記キャップに対し、強制冷却手段が付加されてい
ることを特徴とする請求項１記載の半導体装置。[Claims] 1. A substrate having lead pins erected on one surface thereof and having through holes therein, a multilayer film connected to the through holes and provided on the other surface of the substrate, and bumps. At least one layer mounted on the multilayer film via an electrode
1. A semiconductor device comprising: a semiconductor chip; and a cap soldered to a heat dissipation surface of the semiconductor chip. 2. The semiconductor device according to claim 1, wherein the multilayer film uses polyimide as an insulating material and copper as a wiring material. 3. The semiconductor device according to claim 1, wherein an electronic component is built into the multilayer film. 4. The semiconductor device according to claim 1, wherein forced cooling means is added to the cap.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2149544A JPH0444256A (en) | 1990-06-07 | 1990-06-07 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2149544A JPH0444256A (en) | 1990-06-07 | 1990-06-07 | semiconductor equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0444256A true JPH0444256A (en) | 1992-02-14 |
Family
ID=15477471
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2149544A Pending JPH0444256A (en) | 1990-06-07 | 1990-06-07 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0444256A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6127634A (en) * | 1994-10-11 | 2000-10-03 | Fujitsu Limited | Wiring board with an insulating layer to prevent gap formation during etching |
| US6943443B2 (en) * | 2001-01-17 | 2005-09-13 | Matsushita Electric Industrial Co., Ltd. | Electronic circuit device including metallic member having installation members |
-
1990
- 1990-06-07 JP JP2149544A patent/JPH0444256A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6127634A (en) * | 1994-10-11 | 2000-10-03 | Fujitsu Limited | Wiring board with an insulating layer to prevent gap formation during etching |
| US6943443B2 (en) * | 2001-01-17 | 2005-09-13 | Matsushita Electric Industrial Co., Ltd. | Electronic circuit device including metallic member having installation members |
| US7208833B2 (en) | 2001-01-17 | 2007-04-24 | Matsushita Electric Industrial Co., Ltd. | Electronic circuit device having circuit board electrically connected to semiconductor element via metallic plate |
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