JPH04290258A - Multichip module - Google Patents

Abstract

PURPOSE:To obtain an LSI multichip module whose interconnection length is short, whose signal delay is small and whose density is high by a method wherein ceramic boards on which semiconductor devices have been mounted are connected by organic insulating layers on which internal interconnection patterns have been formed. CONSTITUTION:A semiconductor device 2 is mounted on the surface of a ceramic board 1 where conductor interconnections 10 for a GND, a power supply, a signal and the like have been formed at its inside. A number of ceramic boards 1 required for a module, are stacked organic insulating, and layers 3 are formed between the ceramic boards 1 in order to stack the individual ceramic boards 1. It is desirable that the organic insulating layers 3 are formed of a polyimide resin from the viewpoint of a heat-resistant property, an electric characteristic and a mechanical strength. Interconnection patterns 20 used to electrically connect the ceramic boards 1 to each other at individual stages are formed at the inside of the organic insulating layers 3.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the structure of an LSI multi-chip module, and more particularly to the structure of a multi-chip module used in high-speed data processing systems such as large-scale computers.

0002

2. Description of the Related Art Conventionally, a typical multi-chip module of this type is one in which an LSI is mounted on a printed circuit board or a ceramic substrate. These modules are flat, and electrical connections between each board can be made by arranging the required number of boards in parallel and connecting them with cables, or by connecting the required number of boards to the motherboard with connectors.
It was connected through this motherboard.

In order to improve the performance of high-speed data processing systems such as large-scale computers, it is necessary not only to increase the logic gate switching speed and memory access speed within the LSI, but also to shorten the interconnection length between these LSIs. There is a need. Conventionally, in high-speed data processing systems such as large-sized computers, this interconnection has been realized using multilayer wiring boards. Therefore, how to shorten the mutual wiring length means how to shorten the wiring length within the multilayer wiring board and between the multilayer wiring boards.

[0004] In recent years, the integration of LSIs has particularly progressed, and it has become possible to mount all necessary logic elements on a single multilayer board even in large computers. In fact, it may be more accurate to say that the signal delay between boards is greater than the signal delay within the board, so in order to improve performance, it is necessary to mount everything on a single board.

[0005]

[Problems to be Solved by the Invention] As mentioned above, when creating a one-board system in order to eliminate the wiring length between multilayer wiring boards, the size of the wiring board is determined by the required mounting area for circuit elements such as LSI and external space. It is determined from the required area of input/output terminals for exchanging signals and supplying power. Therefore, the problem is how to shorten the wiring length within the board while securing the necessary area, but conventional planar multilayer wiring boards cannot be said to have sufficient characteristics. In the case of a printed circuit board, elements can be mounted on both the front and back sides, but in this case the input/output terminals have to be placed around the board. Therefore, (1) the distance between the element and the input/output terminal becomes large, and the length of this distribution line becomes long.

(2) The area for input/output terminals is small, and the number of terminals is limited.

[0007] There is a problem.

[0008]

[Means for Solving the Problems] A multi-chip module of the present invention includes a plurality of substrates having conductive wiring patterns and stacked at intervals, a plurality of semiconductor devices mounted on the plurality of substrates, and a plurality of semiconductor devices mounted on the plurality of substrates. The device includes an organic insulating layer formed between the substrates, and a wiring pattern provided in the organic insulating layer to electrically connect the conductor wiring patterns between the substrates.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a sectional view of a multi-chip module according to an embodiment of the present invention.

In FIG. 1, a semiconductor device 2 is mounted on the surface of a ceramic substrate 1 mainly made of alumina or the like and having conductor wiring patterns 10 for GND, power supply, signals, etc. therein. The connection between the semiconductor device 2 and the ceramic substrate 1 differs depending on the type of semiconductor device 2 used.

FIG. 2 shows a structure for attaching various semiconductor devices to the ceramic substrate 1. FIG. 2(a) shows a TAB type semiconductor device 21 having a TAB lead 100.
The TAB lead 100 is Au-Au thermocompression bonded to the ceramic substrate 1. Figure 2 (
The PGA type semiconductor device 22 shown in b) is an I/O
A pin 200 is soldered to the ceramic substrate 1 using Sn/Pb, Au/Sn, or the like. The flip-chip type semiconductor device 23 shown in FIG. 2(c) is attached to the ceramic substrate 1 with solder balls or solder bumps 300. These semiconductor devices 21, 22, 23
can be used depending on the number of pins, power, chip size, etc.

[0013] Ceramic substrates 1 having semiconductor devices 2 mounted thereon are stacked as many times as required by the module to form one multi-chip module structure. An organic insulating layer 3 is formed between the ceramic substrates 1 in order to stack the ceramic substrates 1 together. And this organic insulating layer 3
Polyimide resin is used for its excellent heat resistance, electrical properties, and mechanical strength.

Further, inside the organic insulating layer 3, a wiring pattern 20 is provided for electrically connecting the ceramic substrates 1 at each stage. The thickness of the organic insulating layer 3 varies depending on the density of the internal semiconductor device 2 and the wiring pattern 20, but is usually about 0.5 to 3 mm. In addition, the material for the wiring pattern 20 is C due to the method of connection with the upper and lower ceramic substrates 1 and the workability and adhesion with the organic insulating layer.
u, Au, etc. are used. The connection between the wiring pattern 20 and the ceramic substrate 1 is made by soldering or Au-
Au is bonded by thermocompression.

This multi-chip module can be connected to the outside through pads 31 provided around the lowermost ceramic substrate 11 or pins (not shown) provided on the bottom surface of the ceramic substrate 11.

FIG. 3 is a cross-sectional view of another embodiment of the present invention, in which semiconductor devices 2 are mounted on both the front and back surfaces of the substrate 1 except for the ceramic substrate 11 at the bottom.

When the degree of integration of the entire module increases or a design with severe signal delay is required, a structure in which semiconductor devices 2 are mounted on both the front and back sides of the ceramic substrate 1 as shown in FIG. 3 is also possible.

As a further embodiment of the present invention, as shown in FIG. 4, among the regions between the ceramic substrates 1, only the surrounding region 40 where the semiconductor device 2 is mounted is not formed with the organic insulating layer 3. Take. By doing so, it becomes possible to cool the semiconductor device 2 by passing a heat radiating medium (not shown) through the region 40 as a heat radiating means when a high power semiconductor device 2 is used.

[0019]

Effects of the Invention As explained above, the present invention connects ceramic substrates on which semiconductor devices are mounted with an organic insulating layer having an internal wiring pattern, thereby achieving high performance with short wiring length and extremely small signal delay. A high-density LSI multi-chip module can be realized.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of one embodiment of the present invention.

FIG. 2 is a diagram showing a structure for attaching various semiconductor devices to a ceramic substrate.

FIG. 3 is a cross-sectional view of another embodiment of the invention.

FIG. 4 is a cross-sectional view of yet another embodiment of the invention.

[Explanation of symbols]

1, 11 Ceramic substrate 2, 21, 22, 23 Semiconductor device 3
Organic insulating layer 10 Conductor wiring pattern 20 Wiring patterns 30, 31 Pad 100 TAB lead 200 I/O pin 201 Solder

Claims (3)

[Claims] 1. A plurality of substrates having conductor wiring patterns stacked at intervals, a plurality of semiconductor devices mounted on the plurality of substrates, and an organic insulating layer formed between the substrates. A multi-chip module comprising: a wiring pattern provided in the organic insulating layer and electrically connecting conductor wiring patterns between the substrates. 2. The multi-chip module according to claim 1, wherein semiconductor devices are mounted on both the front and back surfaces of the ceramic substrate. 3. The multi-chip module according to claim 1, wherein the organic insulating layer is not formed only in a region around the semiconductor device.