JPS6110299A - Integrated circuit mounting structure - Google Patents
Integrated circuit mounting structureInfo
- Publication number
- JPS6110299A JPS6110299A JP59131265A JP13126584A JPS6110299A JP S6110299 A JPS6110299 A JP S6110299A JP 59131265 A JP59131265 A JP 59131265A JP 13126584 A JP13126584 A JP 13126584A JP S6110299 A JPS6110299 A JP S6110299A
- Authority
- JP
- Japan
- Prior art keywords
- insulating substrate
- insulating
- integrated circuit
- chip
- insulating substrates
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 77
- 229910000679 solder Inorganic materials 0.000 claims description 9
- 238000002844 melting Methods 0.000 claims description 3
- 230000008018 melting Effects 0.000 claims description 3
- 238000010030 laminating Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 description 7
- 239000000919 ceramic Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
Landscapes
- Combinations Of Printed Boards (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、集積回路チップ（以下、チップと略称する）
全搭載した絶縁基板を互いに重ね合わせて実装するモジ
ュール形式の集積回路装置に関し、特に集積回路モジュ
ールの高密度化全可能にした実装構造に関するものでる
る。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to an integrated circuit chip (hereinafter abbreviated as a chip).
The present invention relates to a module-type integrated circuit device in which all mounted insulating substrates are mounted one on top of the other, and in particular to a mounting structure that enables high-density integrated circuit modules.
近年、ＬＳＩ レベルのチップの高集６［化により各
チツプをセラミックなどの絶縁基板に搭載する実装技術
が高密度化し、それに伴ってモジュール形式の集積回路
装置の実装技術も高密度化が望まれている。In recent years, with the increasing density of LSI-level chips, the mounting technology for mounting each chip on an insulating substrate such as a ceramic substrate has become more dense, and as a result, the mounting technology for module-type integrated circuit devices is also desired to be more dense. ing.
従来のこの種の実装構造の一例を第１図、第２図に示し
て説明すると、第１図および第２図は複数のチップを絶
縁基板上に実装し、この絶縁基板全２層に重ねてモジュ
ール化した実装構造の概略斜視図およびその一部側面断
面図を示す。これらの図において、１はＬＳＩ レベル
の各チップ、２はこれらチップ１を搭載するための信号
および給電用の配線パターンを有するセラミックなどか
らなる実装基板としての絶縁基板、３はこの絶縁基板２
よの周辺罠後述する端子ビンを植設して電気的に接続す
るとともに、機械的に固定するための各々のスルーホー
ル、４ｔ；を前記各々のスルーホール３に挿入してハン
ダ接続され〃・っ電気的接続。An example of a conventional mounting structure of this type is shown and explained in Figs. 1 and 2. In Figs. A schematic perspective view and a partial side sectional view of a mounting structure made into a module are shown. In these figures, 1 is each chip at the LSI level, 2 is an insulating substrate as a mounting board made of ceramic or the like having a signal and power supply wiring pattern for mounting these chips 1, and 3 is this insulating substrate 2.
Terminal pins (described later) are installed in the surrounding traps for electrical connection, and through holes 4t for mechanical fixing are inserted into each of the through holes 3 and connected by soldering. Electrical connection.
機械的な固定を行なう入出力端子としての端子ビンでる
る。なお、第２図中、５は各チップ１と絶縁基板２との
間で溶融し両者を接続しているハンダを示す。A terminal pin is used as an input/output terminal for mechanical fixing. In FIG. 2, numeral 5 indicates solder that is melted between each chip 1 and the insulating substrate 2 to connect them.
第３囚鉱前記絶縁基板２上にチップ１を７エイズ・ダウ
ン実装法にて搭載する方法を示す側面図でろり、チップ
１０表面にはハンダのバンプ６が形成され、また絶縁基
板２の表面にはテップ１の各バンプ６とそれぞれ対応し
てハンダになじむ導電性のパッドγが接続端子として形
成されていて、通常の７エイズ・ダウン実装法にょクチ
ツブ１の表面と絶縁基板２の表面とを対向させて該基板
のパッドＴ上にチップ１の各バンプ６′ｔ−溶融させて
接着されている。This is a side view showing a method of mounting the chip 1 on the insulating substrate 2 by the 7-Aids down mounting method. Conductive pads γ that are compatible with solder are formed as connection terminals in correspondence with each bump 6 in Step 1, and are connected to the surface of the bump 1 and the surface of the insulating substrate 2 using the normal 7-Aids down mounting method. Each bump 6't of the chip 1 is bonded by melting onto the pad T of the substrate with the bumps 6' facing each other.
こ＼で、各チップ１およびスルーホール３間の電気的接
続は、絶縁基板２上に形成した図示しない導体配線パタ
ーンやスルーホールにより行なわれる。そして、高密度
実装するために、前記各絶縁基板２を２層に重ね、共通
に設けた各々のスルーホール３に端子ビン４をそれぞれ
挿入せしめてハンダ接続したうえ、これら端子ビン４に
て各絶縁基板２関全電気的に接続するとともに、機械的
に固定してモジュールを作成する。しかる後、このモジ
ュールに７タ体を装着して樹脂等で気密封止している。Here, electrical connections between each chip 1 and the through holes 3 are made by conductive wiring patterns and through holes (not shown) formed on the insulating substrate 2. In order to perform high-density mounting, the insulating substrates 2 are stacked in two layers, the terminal pins 4 are inserted into the through holes 3 provided in common, and the terminal pins 4 are connected by soldering. The two insulating substrates are electrically connected and mechanically fixed to create a module. Thereafter, the seven-piece body is attached to this module and hermetically sealed with resin or the like.
ところが、上記した従来の実装構造では、以上のように
構成されているので、（Ｉ）各チップ１の真下に端子金
出すことができない。（１１）また、絶縁基板２のスル
ーホールの寸法縮小に限界がろ９、接点数を多くとれな
い。■）各絶縁基板２間の接続と入出力端子金兼ねるた
めに全端子の中でそれぞれの用途で有効に使える端子数
が減少する等の欠点がろり、高密度実装に限度がめった
。However, in the conventional mounting structure described above, since it is configured as described above, (I) it is not possible to provide a terminal directly below each chip 1; (11) Furthermore, there is a limit to the size reduction of the through holes in the insulating substrate 2, making it impossible to increase the number of contacts. (2) Since it serves as a connection between each insulating substrate 2 and an input/output terminal metal, there are drawbacks such as a reduction in the number of terminals that can be effectively used for each purpose out of all the terminals, which limits high-density mounting.
本発明は、このような事情に鑑み、上記した従来の欠点
を除去するためになされたもので、チップを搭載した各
絶縁基板の眉間に、該絶縁基板上の各チップとそれぞれ
対応して穿設された空洞部をＭしかつ信号配線および給
電パターン全形成した接続用絶縁基板を介在せしめて、
これら基板をフリップチップ方式で積層することにより
、実装密度を上げて集積回路モジュールの高密度化を可
能にした実装構造を提供することを目的としている。以
下、本発明の実施例を図について説明する。In view of these circumstances, the present invention has been made to eliminate the above-described drawbacks of the conventional technology. By interposing an insulating board for connection, in which the provided cavity part is M, and signal wiring and power supply patterns are completely formed,
The purpose of this invention is to provide a mounting structure that increases the mounting density by stacking these substrates using a flip-chip method, thereby making it possible to increase the density of integrated circuit modules. Hereinafter, embodiments of the present invention will be described with reference to the drawings.
第４図および第５図は本発明の一実施例による実装構造
を示す一部展開概略斜視図およびその実装形態を示す展
開一部側面断面図であり、第１図乃至第３図と同一また
は相当部分は同一符号を付してるる。これらの図におい
て、２ａは複数のチップ１を７エイズ・ダウンで搭載す
る従来と同様の信号および給電用の配線パターン（図示
せず）を有するセラミックなどからなる絶縁基板、２ｂ
は同じくチップ１を搭載する端子付絶縁基板、４ａはこ
の端子付絶縁基板２ｂ に装着された入出力端子でろる
。FIGS. 4 and 5 are a partially exploded schematic perspective view showing a mounting structure according to an embodiment of the present invention and a partially exploded side sectional view showing its mounting form, and are the same as or similar to FIGS. Corresponding parts are given the same symbols. In these figures, 2a is an insulating substrate made of ceramic or the like having a signal and power supply wiring pattern (not shown) similar to the conventional one, on which a plurality of chips 1 are mounted 7A down, and 2b
Similarly, numeral 4a denotes an insulating board with a terminal on which the chip 1 is mounted, and input/output terminals mounted on the insulating board 2b with a terminal.
また、２ｃは前記各絶縁基板２ａ＋９Ｉａ子付絶縁基板
２ｂ上に搭載される各チップとそれぞれ対応して穿設さ
れた正方形状の空洞部１１を有しかつ信号および給電用
の配線パターン（図示せず）を有するセラミックなどか
らなる接続用絶縁基板、６ａは前記各絶縁基板２ａ と
接続用絶縁基板２ｃの底面にそれぞれ形成されたハンダ
のバンプ、γａは前記絶縁基板２ａと端子付接続基板２
ｂおよび接続用絶縁基板２ｃの各々の表面に形成された
ハンダになじむ導電性のパッドでるる。Further, 2c has a square cavity 11 bored corresponding to each chip mounted on each insulating substrate 2a+9Ia and insulating substrate 2b with a child, and has a wiring pattern for signal and power supply (not shown). 6a is a solder bump formed on the bottom surface of each of the insulating substrates 2a and the connecting insulating substrate 2c, and γa is a bond between the insulating substrate 2a and the terminal-equipped connecting substrate 2.
There are conductive pads that are compatible with the solder formed on the surfaces of the connecting insulating substrate 2c and the connecting insulating substrate 2c.
なお、第６図は、複数のチップ［−搭載した絶縁基板２
ａの側面図を示し、この絶縁基板２ａの底面にバンプ６
ａが、その表面にパッド１ａ がそれぞれ形成されてい
る。また、第７図は絶縁基板２８問および絶縁基板２ａ
と端子付絶縁基板２ｂ間に介在してそれら各層間を接
続する接続用絶縁基板２ｃの側面図全示し、下層側の絶
縁基板上に搭載される各々のチップ１と対応した空言部
１１が買通して穿設され、その底面にバンプ６ａが、表
面にバッド７ａ がそれぞれ形成されている。In addition, FIG. 6 shows a plurality of chips [- mounted insulating substrate 2
Bumps 6 are shown on the bottom surface of this insulating substrate 2a.
A pad 1a is formed on the surface of each pad 1a. In addition, FIG. 7 shows 28 questions on the insulating substrate and the insulating substrate 2a.
A side view of the connecting insulating substrate 2c interposed between the terminal-attached insulating substrate 2b and connecting the respective layers is shown, and the blank portions 11 corresponding to the respective chips 1 mounted on the lower layer side insulating substrate are shown. A bump 6a is formed on the bottom surface of the hole, and a pad 7a is formed on the surface thereof.
さらに、第８図は各絶縁基板を積層する最下層としての
各チップ１を搭載した端子付絶縁基板２ｂの側面図を示
し、その底面に入出力端子４ａが装着され、表面にバッ
ド７ａが形成されている。Furthermore, FIG. 8 shows a side view of the insulating board 2b with terminals mounted with each chip 1 as the lowest layer of laminating the insulating boards, with input/output terminals 4a attached to the bottom surface and a pad 7a formed on the surface. has been done.
しかして、各絶縁基板２ａ 、 ２ｂおよび接続用絶縁
基板２ｃ ｋ互いに重ねて積層する場合、第６図に示す
チップ１全搭載した絶縁基板２ａ と第７図に示す接続
用絶縁基板２Ｃを交互に重ね合わせ、最下層に第８図に
示すチップ１を搭載した端子付絶縁基板２ｂ ｋ重ね合
わせることにより、第４図および第５図に示すように、
チップ１全搭載した絶縁基板２ａ間と該絶縁基板２ａ、
端子付絶縁基板２ｂ間の各々の層間に接続用絶縁基板２
Ｃが介在され、これら接続用絶縁基板２ｃｋ通じて前記
各絶縁基板２ａ 、 ２ｂ間を相互に接続して実装する
ことができる。Therefore, when the insulating substrates 2a, 2b and the connecting insulating substrate 2c are stacked on top of each other, the insulating substrate 2a shown in FIG. 6 with all the chips 1 mounted thereon and the connecting insulating substrate 2C shown in FIG. 7 are alternately stacked. As shown in FIGS. 4 and 5, as shown in FIGS.
Between the insulating substrate 2a on which the chip 1 is fully mounted and the insulating substrate 2a,
Insulating substrate 2 for connection between each layer between insulating substrates with terminals 2b
C is interposed, and the insulating substrates 2a and 2b can be mutually connected and mounted through these connection insulating substrates 2ck.
このとき、各チップ１とバンプ６ａおよびノ（ラド７ａ
の間の電気的接続は、絶縁基板２ａ と端子付絶縁基
板２ｂにそれぞれ形成した配線パターンやスルーホール
により行なう。また、接続用絶縁基板２ｃ は、第１図
および第２図に示す従来例での端子ビン４に代って、絶
縁基板２８間ならびに絶縁基板２ａ と端子付絶縁基板
２ｂの間に挾み込まれ、両者を機械的に固定しかつ電気
的に接続するだけでなく、信号および給電用配線パター
ンやスルーホール全形成することにより、信号配線や給
電にも利用できる。また、各々のバンプ６ａ とバッド
７ａはハンダを溶融させることにより、各絶縁基板２ａ
と２ｂおよび２ｃｔ互いに７リツプチツプ法にて接続す
るものでろり、このハンダ接続点において各絶縁基板間
の信号の入出力や給電を行ない、かつ機械的に固定する
ものとなっている。At this time, each chip 1, bump 6a and no (rad 7a)
Electrical connection between them is made by wiring patterns and through holes formed on the insulating substrate 2a and the insulating substrate with terminals 2b, respectively. In addition, the connection insulating substrate 2c is inserted between the insulating substrates 28 and between the insulating substrate 2a and the insulating substrate with terminals 2b, instead of the terminal pin 4 in the conventional example shown in FIGS. 1 and 2. In rare cases, it can be used for signal wiring and power supply by not only mechanically fixing and electrically connecting the two, but also by forming all signal and power supply wiring patterns and through holes. In addition, each bump 6a and pad 7a are formed by melting solder on each insulating substrate 2a.
, 2b and 2ct are connected to each other by the 7-lip chip method, and at these solder connection points, signals are input/output and power is supplied between the respective insulating substrates, and they are mechanically fixed.
なお、かかる絶縁基板を互いに積層して集積回路モジュ
ールを実装したうえ、従来と同様にこのモジュールにフ
タ体全装着し、かつ樹脂等で気密封止して作成される。Incidentally, such insulating substrates are laminated on each other to mount an integrated circuit module, and a lid body is entirely attached to this module as in the conventional case, and the module is hermetically sealed with resin or the like.
このように、上記実施例によれば、チップを搭載した絶
縁基板間に、該絶縁基板上の各チップとそれぞれ対応し
て空洞部が穿設されかつ信号配線や給電用パターンが形
成された接続用絶縁基板をフリップチップ方式で積層し
て実装することにより、上記した従来のものに比べて、
接続端子数全長くとることができるとともに、回路の実
装密度を高め、かつ装置の小型化が可能になる。As described above, according to the above embodiment, a connection is made in which cavities are formed between insulating substrates on which chips are mounted, corresponding to each chip on the insulating substrate, and signal wiring and power supply patterns are formed. By stacking and mounting insulating substrates using the flip-chip method, compared to the conventional ones mentioned above,
The total number of connection terminals can be increased, the circuit packaging density can be increased, and the device can be made smaller.
なお、上記実施例では接続用絶縁基板２Ｃに形成する各
チップに対応した空洞部１１を正方形状に穿設したが、
その形状は任意に形成でき、要は絶縁基板上に搭載され
る各々のチツプを挿入可能な形状でろ九ばよい。In addition, in the above embodiment, the cavity 11 corresponding to each chip formed on the connection insulating substrate 2C is bored in a square shape.
The shape can be formed arbitrarily, and in short, the shape should be such that each chip mounted on the insulating substrate can be inserted thereinto.
また、端子付絶縁基板２ｂに装着する入出力端子４ａ
ｋプラグイン・パッケージの端子形状で示したが、フラ
ット・パッケージやリードレス・チップキャリアの端子
形状でろうても、その他どのような形状にしても同様の
効果を奏する。In addition, an input/output terminal 4a attached to the insulating board with terminal 2b
Although the terminal shape is shown using a plug-in package, the same effect can be achieved even if the terminal shape is a flat package, a leadless chip carrier, or any other shape.
以上説明したように、本発明は、チップを搭載した絶縁
基板を重ね合わせて実装するものにおいて、前記各絶縁
基板の層間に、該絶縁基板上に搭載された各チップとそ
れぞれ対応して穿設された空洞部を有する接続用絶縁基
板を介在させることにより、この接続用絶縁基板全通じ
て前記各絶縁基板間を相互に接続して実装するようにし
たので、接続端子数を増大させることができるとともに
、集積回路モジュールの実装密度を高め、かつ装置の小
型化が可能となり、従って、安価で性能の良い集積回路
モジュールを製造することができる効果がろる。As explained above, the present invention provides a device in which insulating substrates on which chips are mounted are stacked and mounted, in which holes are formed between the layers of each insulating substrate, corresponding to each chip mounted on the insulating substrate. By interposing the connecting insulating substrate having a hollow portion, the insulating substrates are connected to each other through the entire connecting insulating substrate, so that the number of connection terminals can be increased. At the same time, it becomes possible to increase the packaging density of integrated circuit modules and to reduce the size of the device.Therefore, it is possible to manufacture integrated circuit modules with good performance at low cost.
第１図および第２図は従来例による実装構造を示す概略
斜視図およびその一部側面断面図、第３図は第１図の絶
縁基板上にチップをフェイズ・ダウン実装法にて搭載す
る形態を示す側面図、第４図および第５図は本発明の一
実施例による実装構造を示す一部展開概略斜視図および
その形ａｔ−示す展開一部側面断面図、第６図、第７図
および第８図は上記実施例における絶縁基板、端子付絶
縁基板および接続用絶縁基板をそれぞれ示す側面図でめ
る。
１・・・・チップ、２ａ ・・・・絶縁基板、２ｂ・
・・・抱子付絶縁基板、２Ｃ・・・・接続用絶縁基板、
４ａ・・・・入出力端子、５＠・Φ・ハンダ、６ａ
・−ｍｅバンフ’、７ａ ＠・―・パッド、１１・・
・・空洞部。1 and 2 are schematic perspective views and a partial side cross-sectional view of a conventional mounting structure, and FIG. 3 is a configuration in which a chip is mounted on the insulating substrate shown in FIG. 1 using the phase-down mounting method. FIGS. 4 and 5 are a partially exploded schematic perspective view showing a mounting structure according to an embodiment of the present invention, and a partially exploded side sectional view showing its shape, FIGS. 6 and 7. and FIG. 8 is a side view showing an insulating substrate, an insulating substrate with a terminal, and an insulating substrate for connection in the above embodiment, respectively. 1...Chip, 2a...Insulating substrate, 2b...
... Insulating board with clasp, 2C... Insulating board for connection,
4a...Input/output terminal, 5@・Φ・Solder, 6a
・-me Banff', 7a @・・・Pad, 11...
・Cavity part.
Claims (2)
て実装するものにおいて、前記各絶縁基板の層間に、該
絶縁基板上に搭載された各集積回路チツプとそれぞれ対
応して穿設された空洞部を有する接続用絶縁基板を介在
させることにより、この接続用絶縁基板を通じて前記各
絶縁基板間を相互に接続して実装するようにしたことを
特徴とする集積回路実装構造。(1) In a device in which insulating substrates on which integrated circuit chips are mounted are stacked and mounted, cavities are bored between the layers of each insulating substrate, corresponding to each integrated circuit chip mounted on the insulating substrate. An integrated circuit mounting structure characterized in that the respective insulating substrates are interconnected and mounted through the intervening insulating substrate for connection having a portion.
各絶縁基板に信号配線パターンおよび給電パターンをそ
れぞれ形成し、かつ前記各絶縁基板間を電気的に接続す
るとともに機械的に固定するために、その一方の絶縁基
板にはハンダのバンプを、他方の絶縁基板にはこれを受
けるパツドをそれぞれ形成し、これら絶縁基板を互いに
重ねてハンダを溶融させて接着することを特徴とする特
許請求の範囲第１項記載の集積回路実装構造。(2) When laminating the respective insulating substrates, in order to form a signal wiring pattern and a power supply pattern on each of these insulating substrates, and to electrically connect and mechanically fix the respective insulating substrates, Claims characterized in that one of the insulating substrates is formed with solder bumps, and the other insulating substrate is formed with pads for receiving the bumps, and these insulating substrates are stacked on top of each other and bonded by melting the solder. The integrated circuit mounting structure according to item 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59131265A JPS6110299A (en) | 1984-06-26 | 1984-06-26 | Integrated circuit mounting structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59131265A JPS6110299A (en) | 1984-06-26 | 1984-06-26 | Integrated circuit mounting structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6110299A true JPS6110299A (en) | 1986-01-17 |
Family
ID=15053881
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59131265A Pending JPS6110299A (en) | 1984-06-26 | 1984-06-26 | Integrated circuit mounting structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6110299A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62224958A (en) * | 1986-03-19 | 1987-10-02 | ヒエミ− ウント フイルタ− ゲゼルシヤフト ミツト ベシユレンクタ− ハフツング | Electronic device with mutually laminated modules |
| JPH01118456U (en) * | 1988-02-04 | 1989-08-10 | ||
| JPH021962A (en) * | 1988-06-10 | 1990-01-08 | Mitsubishi Electric Corp | Semiconductor device |
| JPH0393258A (en) * | 1989-08-31 | 1991-04-18 | Hughes Aircraft Co | Three-dimensional integrated circuit construction using discrete chip |
| JPH04290258A (en) * | 1991-03-19 | 1992-10-14 | Nec Corp | Multichip module |
| JP2002124622A (en) * | 2000-08-21 | 2002-04-26 | Kankoku Joho Tsushin Gakuen | Multi-chip module made of low-temperature fired ceramic and its mounting method |
| JP2008525731A (en) * | 2004-12-23 | 2008-07-17 | ベーエスハー ボッシュ ウント ジーメンス ハウスゲレーテ ゲゼルシャフト ミット ベシュレンクテル ハフツング | Valve device |
| JPWO2015151292A1 (en) * | 2014-04-04 | 2017-04-13 | 三菱電機株式会社 | Printed wiring board unit |
-
1984
- 1984-06-26 JP JP59131265A patent/JPS6110299A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62224958A (en) * | 1986-03-19 | 1987-10-02 | ヒエミ− ウント フイルタ− ゲゼルシヤフト ミツト ベシユレンクタ− ハフツング | Electronic device with mutually laminated modules |
| JPH01118456U (en) * | 1988-02-04 | 1989-08-10 | ||
| JPH021962A (en) * | 1988-06-10 | 1990-01-08 | Mitsubishi Electric Corp | Semiconductor device |
| JPH0393258A (en) * | 1989-08-31 | 1991-04-18 | Hughes Aircraft Co | Three-dimensional integrated circuit construction using discrete chip |
| JPH04290258A (en) * | 1991-03-19 | 1992-10-14 | Nec Corp | Multichip module |
| JP2002124622A (en) * | 2000-08-21 | 2002-04-26 | Kankoku Joho Tsushin Gakuen | Multi-chip module made of low-temperature fired ceramic and its mounting method |
| JP2008525731A (en) * | 2004-12-23 | 2008-07-17 | ベーエスハー ボッシュ ウント ジーメンス ハウスゲレーテ ゲゼルシャフト ミット ベシュレンクテル ハフツング | Valve device |
| JPWO2015151292A1 (en) * | 2014-04-04 | 2017-04-13 | 三菱電機株式会社 | Printed wiring board unit |
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