JPH0423049A - Bus cycle re-executing method - Google Patents

Abstract

PURPOSE:To suppress the bus errors caused by a high speed operation at re- execution of a bus cycle and to carry out a correct bus cycle by reducing the bus cycle executing conditions including the operating frequency, the wait frequency, etc., in re-execution of the bus cycle. CONSTITUTION:In a normal cycle state, a microprocessor MPU 1 executes the bus cycles among the clocks S0 - S7. A bus error detecting part 2 detects an error of a system bus 6 and outputs an error signal 7. The MPU 1 receives the signal 7 and completes the bus cycle under execution to execute again the bus cycle after holding it once. Then the MPU 1 basically executes again the bus cycles up to the clocks S0 - S7. In this case, however, the MPU 1 puts a wait state SW between the clocks S4 and S5. As a result, the bus cycle time is increased and therefore the bus cycle executing conditions are reduced. Then the bus errors caused by a high speed operation can be suppressed at the time of re-execution of the bus cycle.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bus cycle re-execution method in a computer system for detecting and dealing with bus errors.

[Conventional technology]

In recent years, computer systems have been widely applied in various fields. This computer system.

Data necessary for processing is stored in RAM. Therefore,
RAM needs to have high reliability to prevent improper processing. Furthermore, for buses where data and the like are exchanged, accurate execution of bus cycles is essential, and it is necessary to detect and deal with bus errors.

Therefore, the MPU used in conventional computer systems is Hitachi's 6800.68000 series microprocessor/peripheral LSI data book (198
9) As shown in the re-execution bus cycle timing shown in FIG. 24 on page 307, when a bus error is detected, the bus cycle is re-executed under the same bus cycle execution conditions as when the bus error was detected.

[Problem to be solved by the invention]

However, in recent years, as the performance of computer systems has improved, bus cycles have become faster, and there has been a problem in that bus errors caused by this faster speed also occur during re-execution.

SUMMARY OF THE INVENTION An object of the present invention is to provide a computer system that can suppress bus errors caused by speeding up during re-execution and execute correct bus cycles.

[Means to solve the problem]

As a means for achieving the above object, bus cycle execution conditions such as the operating frequency and the number of waits are relaxed when the bus cycle is re-executed.

[Effect]

By relaxing the bus cycle execution conditions when re-executing the bus cycle as described above, margins such as set-up time and hold time of the data bus and bus control signals between the MPU and external devices such as RAM can be reduced. You can make it bigger.

Therefore, bus errors caused by speeding up can be suppressed during re-execution, and correct bus cycles can be executed.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1, 2, and 3.

FIG. 1 shows a flowchart of a bus cycle re-execution method according to an embodiment of the present invention.

In step 1, a normal bus cycle is executed.

Step 12 It is determined whether or not a bus error has occurred in the execution of the bus cycle in step 11. Also, if no error occurs, the process is terminated, and if an error occurs, step 13 is executed.
Branch to processing.

Step 13: Relax the bus cycle execution conditions by lowering the operating frequency or increasing the number of waits, and re-execute the bus cycle.

Step 14: It is determined whether or not a bus error has occurred with respect to the bus cycle execution of step 13. Further, if no error occurs, the process ends, and if an error occurs, the process branches to bus error exception processing. Here, what is bus error exception handling?
This refers to the processing that a computer system performs in response to a bus error, and generally notifies the user of the bus error and halts the entire system.

Next, bus cycle execution will be explained with reference to FIGS. 2 and 3.

FIG. 2 shows a block diagram of a computer system according to an embodiment of the present invention.

Block 1 is an MP that performs sequence control of the entire system.
U, block 2 is a bus error detection unit that detects system bus errors, block 3 is a memory that stores programs and data, block 4 is an I10 device 1 that is a peripheral device of M Fl t, J, and block 5 is an MPU. The I10 device 2 which is another peripheral device, the block 6 is a system bus connecting each block, and the block 7 is an error signal which is an output signal of the bus error detection section 2.

FIG. 3 shows the bus cycle timing when the bus cycle is re-executed in one embodiment of the present invention.

During the normal cycle shown on the left side of the figure, MPU1
A bus cycle is executed from 0 to 87.

However, as shown in Figure 1, when the bus error detection unit 2 detects an error on the system bus 6 and outputs the error error signal 7, the MPUI that receives this ends the bus cycle being executed, and After entering the halt state, a re-execution cycle is performed.

Even in the re-execution cycle shown on the right side of the figure, basically the MPU
1 re-executes the previous bus cycle from SO to 87. However, during re-execution, in order to suppress bus errors, the MPU inserts a wait state (SW) between S4 and S5 to lengthen the bus cycle in order to relax the bus cycle execution conditions. ing.

In this embodiment, the bus cycle execution conditions are relaxed by inserting a wait state at the time of re-execution, but the bus cycle execution conditions may be relaxed by lowering the operating frequency or the like.

Further, in this embodiment, bus cycle execution conditions are relaxed by the MPU, but this may be done by other means. Furthermore, in this embodiment, the bus error detection section is separated from the MPU, but the bus error detection section may be located within the MPU.

According to this embodiment, margins such as set-up time and hold time for data buses and bus control signals between the MPU and external devices such as RAM can be increased. Therefore, bus errors caused by speeding up can be suppressed during re-execution, and correct bus cycles can be executed.

〔Effect of the invention〕

According to the present invention, bus errors caused by speeding up can be suppressed during re-execution, and correct bus cycles can be executed.

[Brief explanation of drawings]

FIG. 1 is a flowchart of a bus cycle re-execution method according to an embodiment of the present invention, FIG. 2 is a block diagram of a computer system according to an embodiment of the present invention, and FIG. 3 is a bus cycle re-execution method according to an embodiment of the present invention. An explanatory diagram of bus cycle timing during execution is shown. 1...MPU, 2...Bus error detection unit, 3...
Memory, 4... Engineering/○ device, 5... I10 device, 6... System bus, 7... Error signal. 1 illustration

Claims (1)

[Scope of Claims] 1. A bus cycle re-execution method in a computer system that re-executes a bus cycle upon detection of a bus error, characterized in that conditions for executing the bus cycle at the time of re-execution are relaxed.