JPS63216173A - Command transfer control device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] For example, in a vector processing device, a vector instruction is transferred from a scalar unit to a vector unit.

Execute vector instructions in the vector unit. When a vector instruction is sent, if an error occurs at the end of the pipeline in the scalar unisoto, the transfer of the vector instruction cannot be stopped, so execution of this instruction will start. The present invention adds an identifier to an instruction in a vector unit, and provides means for canceling an instruction in which an error has occurred and an instruction whose transfer is interrupted in the middle based on this identifier, thereby making it possible to cancel multiple instructions. , allows instructions to be retried (re-executed) in response to errors.

[Industrial application field]

The present invention may be applied to a vector processing device, for example.

It relates to a device that transfers instructions from one instruction execution unit to another instruction execution unit, and in particular, an instruction that continuously transfers instructions to be executed by another instruction execution unit divided into multiple opcodes/data. The present invention relates to a transfer control device.

When an error related to an instruction occurs in a data processing device or the like, it is often possible to recover by retrying the instruction. It is desirable to be able to perform retries in response to such intermittent failures, regardless of the timing of error occurrence, even in vector processing devices that continuously receive instruction transfers.

[Conventional technology]

For example, a vector processing device includes a scalar unit (SU) that processes scalar instructions and a vector instruction unit (VU) that processes vector instructions. If there is a vector instruction, the scalar unit transfers the instruction to the vector unit via the pipeline, and the vector unit executes the received vector instruction.

Conventionally, if an error in an instruction is detected in the scalar unit just before the instruction is transferred from the scalar unit to the vector unit, the transfer cannot be stopped due to the timing, so the vector unit
It will start executing that command. Therefore, in the scalar unit.

The instruction that caused the error could not be tried. That is, when such an error occurs, if the instruction is tried again, the same vector instruction will be executed twice in the vector unit depending on the timing, resulting in a logical contradiction.

[Problem that the invention seeks to solve]

While there is a tendency for vector processing equipment to be highly reliable, the scalar unit of vector processing equipment is
Since vector instructions are also highly controlled, the amount of microprograms tends to increase, and errors in the RAM for microprograms are more likely to occur. In other words, despite the strong demand for high reliability,
The occurrence of errors tends to increase due to higher performance and functionality, and a solution to this problem is desired.

In vector processing devices, etc. that continuously transfer instructions, most errors related to transferred instructions occur in RAM.
These errors can often be corrected by retrying. Therefore, regarding errors that occur in the SCARA unit, no matter when the error occurs,
Instructions that should be inhibited from being executed after being transferred to the vector unit are
It is desirable to be able to cancel everything and retry.

The present invention aims to solve the above problem, and when a hardware failure occurs in the pipeline of the first instruction execution unit, the instruction canceled in the first instruction execution unit is transferred to the second instruction execution unit to which the instruction is transferred. , the purpose is to provide a means to cancel everything and retry the command.

[Means for solving problems] FIG. 1 is a block diagram of the principle of the present invention.

In FIG. 1, 10 is a first instruction execution unit that transfers instructions, 11 is a second instruction execution unit that executes transferred instructions, and 12 is an instruction transfer circuit 513 that transfers instructions.
An error signal transmission circuit transmits an error signal to the second instruction execution unit 11.

14 is a register that receives the transferred instruction; 15 is an ID field that stores an instruction identifier (ID) added to the received instruction; 16 is an instruction ID generation counter that adds an instruction identifier to the received instruction; 17 is the received instruction. An instruction holding circuit 18 holds instructions, and 18 is a circuit (18) that stores instruction identifiers of instructions for which error occurrence may be notified.
D register, 19 is a time monitoring circuit that monitors the time until the final timing when an error signal is sent, 20 is a transfer interruption detection circuit that detects that instruction transfer is interrupted midway, 21
22 represents an error instruction canceling circuit that cancels an instruction in which an error has occurred, and an interrupted instruction canceling circuit that cancels an instruction whose transfer is interrupted midway.

#12 divides the instruction to be executed by the IMF execution unit 11 into a plurality of operation codes/data and transfers them according to the instruction vibe line. Second instruction execution unit 11
receives the transferred instruction into register 14, and
The count value of the instruction ID generation counter 16 is set in the ID field 15.

The count value of the instruction ID generation counter 16 is updated for each new instruction.

The instruction holding circuit 17 is constituted by several stages of buffer registers, and holds the transferred instruction together with the instruction identifier until the instruction is issued. The time monitoring circuit 19 is a counter that monitors each instruction for two hours until the final timing at which an error signal may be sent from the first instruction execution unit 10.

In the first instruction execution unit 10, when an error signal arrives during time monitoring by the 0 time monitoring circuit 19 which is transmitted to the machining line unit 11, the error instruction canceling circuit 21 is activated. The error instruction cancellation circuit 21 is
Contents of current ID register 18 and instruction holding circuit 17
It compares the instruction identifier added to each opcode/data of the instruction held in the instruction holding circuit 17, and if they match, outputs a cancel signal to invalidate the instruction held in the instruction holding circuit 17.

The transfer interruption detection circuit 20 detects the transfer of instructions to be continuously sent from the first instruction execution unit 10.

If the instruction is interrupted midway, it is detected and the interruption instruction canceling circuit 22 is operated. Interruption command cancellation circuit 2
2 compares the instruction identifier of the interrupted instruction with the instruction identifier added to each opcode/data of the instruction held in the instruction holding circuit 17, and if they match, the instruction holding circuit 17 holds it. A cancel signal is output in response to that command.

[Effect]

From the first instruction execution unit 10 to the second instruction execution unit 1
According to the conventional method, when an instruction is transferred separately into an operation code and data, if an error in that instruction or an error in a subsequent instruction occurs in the latter half of the pipeline of the first instruction execution unit 10, the timing It is not possible to stop the transfer of commands depending on the timing.

Subsequent instructions are also transferred halfway.

According to the invention, for the opcode/data of the instruction received by the second instruction execution unit 11.

An instruction identifier is added by the instruction ID generation counter 16 and held in the instruction holding circuit 17 until the instruction is issued.

Also provided is a time monitoring circuit 19 that guarantees the timing of arrival of an error signal for each instruction. When an error signal is sent, the error instruction canceling circuit 21 selects the instruction corresponding to the signal using the instruction identifier and cancels it. Furthermore, even if the transfer of one instruction is interrupted midway through, the interrupted instruction canceling circuit 22 cancels that instruction based on the instruction identifier.

Therefore, in the second instruction execution unit 11.

Multiple instructions related to the error can be canceled, and after the cancellation is completed, the first instruction execution unit lO
, it becomes possible to perform a command transfer trial.

〔Example〕

FIG. 2 shows an example of a system to which the present invention is applied, FIG. 3 shows an embodiment of the present invention, and FIG. 4 shows a time chart of an embodiment of the present invention.

FIG. 2 shows an example of a vector processing device to which the present invention is applied. In FIG. 2, 30 is a main memory device, 31 is a main memory control device, 32 is a scalar unit that processes scalar instructions, 33 is a vector unit that processes vector instructions, and 34 is a vector instruction control unit that controls vector instructions. , 35 is a vector instruction execution unit that executes vector instructions, 36 is a load pipeline, 37 is a store pipeline, 38 is a vector register 939 for storing vector data is an addition pipeline, 40 is a multiplication pipeline, 41 is the division pipeline, 42.4
3 represents an internal signal line.

The scalar unit 32 is from the main storage device 30.

Scalar instructions and vector instructions are read out via the main memory controller 31. Vector instructions are scalar unisoto32
The signal flows through the pipeline and is transferred to the vector unit 33. The instructions transferred.

When the vector instruction control unit 34 in the vector unit 33 receives the instruction and it is time to execute the instruction, the vector instruction execution unit 35 receives a signal '
The start of the instruction is applied through 4IA42. The vector instruction execution unit 35.

A signal line 43 sends a signal indicating that an instruction is being executed to the vector instruction control unit 34 for each pipeline 39, 40, 41. The vector instruction control unit 34 starts instructions when these pipelines become available, that is, when the signal of the corresponding pipeline on the signal line 43 turns OFF. Associated with the vector command control unit 34.

FIG. 3 shows a portion of the circuitry within the vector instruction control unit 34.

In FIG. 3, 50 is a fetch stage register (V
FS), which corresponds to the register 14 shown in FIG. 1, 51 is a fetch buffer register (VFB), and 52 is a virtual decoding stage register 9 (VPS).

, :[VFB51. The VPS 52 corresponds to the instruction holding circuit 17 shown in FIG.

53 is a VFR cancel circuit, and 54 is a VPS cancel circuit. 55 is an instruction interruption detection circuit in VFS, which corresponds to the transfer interruption detection circuit 20 shown in FIG.

56 is a timing counter, which corresponds to the time monitoring circuit 19 shown in FIG.

60 is a data bus.

Ll and L4-L6 are latches, L2 and L3 are SE
T/RESET latch, R1 to R3 are registers, C1~
C4 is a one-digit circuit, Al to A5 are AND circuits, OR1
~OR4 represents an OR circuit.

In scalar unisoto, as shown in FIG. 4, a vector instruction is executed in four flows, and from the T state of the final flow, operation code IVI, operation code IV2. data DV
1. It is assumed that vector instructions are successively transferred to the vector unit in the order of data DV2.

By executing the vector instruction in the scalar unit, opcode IVI, opcode IV2 . Data DV 1. Data DV2 is 1τ
VALI (machine cycle) is displayed to indicate validity.
D signal is turned ON.

In the vector unit, by the VALTD signal.

At the same time as latch L1 is set, an enable signal is input to register R1, and the opcode/data of the instruction sent via data bus 60 is received. The instruction ID generation counter 16 generates an instruction identifier for each instruction, and stores it in the ID field of register R1 to be added to each opcode/data.

The opcode/data and instruction identifier of this VFS 50 are stored when the VPS 52 is vacant.

To the VPS52, if the VPS52 is clogged, ■
Sent to FB51. In addition, VFB51.

Although the illustration is simplified, the structure may be multi-staged if necessary. The principle is the same even when there are multiple stages.

At the same time as the timing counter 56 operates at the timing of the VA and LID signals for data DV2, VFS
50 is set in the current ID register 18. That is, the current ID register 18 holds an instruction identifier related to the operation of the timing counter 56.

For example, at the ERR timing shown in Figure 4.

Assume that an error occurs in either vector instruction v1 or vector instruction v2. At this timing, all of vector instruction (1) is transferred to the vector unit, and vector instruction (V2) is also transferred to the vector unit by operation code IVI. In this case, since the scalar unit tries to retry starting from the vector instruction (1), it is necessary to cancel the two vector instructions v1 and V2 in the vector unit.

This is done as follows.

In SCARA UNISOTO, when an error occurs in the pipeline, the error latch is turned ON and then a machine check detection signal is sent to the vector unit indicating that a hard error has been detected in SCARA UNISOTO.

In the vector unit, TI, T2 . When the machine check detection signal is received during the time monitoring of T3, the output of the AND circuit A5 becomes "1", and the VFB cancel circuit 53 and the PS cancel circuit 54 operate. VFB cancel circuit 53. The VPS cancel circuits 54 each have a current ID register 1.
Based on the instruction identifier held by 8, this and VFB51
By comparing the instruction identifier held by the VFS 52, an instruction to be canceled is found, and a cancel signal is output to the register holding the corresponding instruction. This cancel signal is applied to the SET/RESET latch L
2. By resetting L3, the instruction held by the register is invalidated.

Furthermore, at the timing shown in FIG.

Since the next vector instruction V2 is also partially transferred to the vector unit, it is similarly canceled. Therefore, when the VFS instruction discontinuity detection circuit 55 detects an instruction transfer discontinuity, it inputs the detection signal to the VFB cancel circuit 53 and the PS cancel circuit 54. V
FB cancel circuit 53. The VPS cancel circuit 54 searches for an interrupted instruction based on the instruction identifier possessed by each VFS 50, and if there is a corresponding interrupted instruction, sends a cancel signal to the VFB 5t and VFS 52.

In addition, the 5 vector unit sends a busy signal (VU Busy) indicating that an instruction remains in the vector unit.

It is now possible to notify Scala Uninote. The output of the OR circuit OR4 is its busy signal.

From the vector instruction execution unit 35 shown in FIG.

Is there a signal (Execute) indicating that the command is being executed?

Or, if any one of latches 1 to L3 is ON, it becomes "1".

In the scalar unit, when an error occurs, the interrupt processing is started, but while the above busy signal is “1”,
Makes the start of interrupt processing wait.

As a result, the instruction completion order within the hector unit is correct for instructions in which a hard error has occurred, and all instructions that are canceled within the scalar unit due to a hard error within the scalar unit are also canceled within the vector unit. Therefore, it is possible to correctly perform instruction transfer trials.

〔Effect of the invention〕

As explained above, according to the present invention, before the instruction issuing control stage of the second instruction execution unit.

In a system that can continuously accept transfers of instructions from the first instruction execution unit by having a bus flow, an error occurs in the first instruction execution unit and an instruction to be canceled in the scalar unit is canceled. ,
Even if a plurality of instructions have already been transferred to the second instruction execution unit, it becomes possible for the second instruction execution unit to cancel all of those instructions. This makes it possible to try out commands, so high reliability can be achieved even in systems that speed up the transmission of commands.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is an example of a system to which the present invention is applied, FIG. 3 is an embodiment of the present invention, and FIG. 4 is a time chart of an embodiment of the present invention. In the figure, 10 is a first instruction execution unit, 11 is a second instruction execution unit, 12 is an instruction transfer circuit, 13 is an error signal transmission circuit, 14 is a register, 15 is an ID field, 16
1 is an instruction ID generation counter, 17 is an instruction holding circuit, and 18 is a current ID register. 19 is a time monitoring circuit, and 20 is a transfer interruption detection circuit. 21 represents an error instruction cancellation circuit, and 22 represents an interruption instruction cancellation circuit.

Claims (1)

[Claims] From the first instruction execution unit (10) to the second instruction execution unit (11), the instructions to be executed by the second instruction execution unit (11) are divided into a plurality of opcodes/data and are successively transmitted. In the information processing apparatus, the first instruction execution unit (10) transmits an error signal to the second instruction execution unit (11) when an error related to the instruction to be transferred is detected. Transmission means (13)
The second instruction execution unit (11) includes instruction ID generation means (11) for adding an instruction identifier to each opcode/data of the instruction transferred from the first instruction execution unit (10).
16); an instruction holding means (17) for holding each opcode/data of the transferred instruction together with an attached instruction identifier; a time monitoring means (19) for monitoring time until the final timing at which an error signal is sent from the unit (10);
When an error signal is sent from , by comparing the instruction identifier of the instruction in which the error occurred and the instruction identifier of each operation code/data held by the instruction holding means (17),
An error instruction canceling means (21) generates a cancellation signal for the corresponding instruction, and when it is detected that instruction transfer is interrupted midway, the instruction identifier of the interrupted instruction and each instruction held by the instruction holding means (17) are stored. Interruption instruction canceling means (2) that generates a cancellation signal for the corresponding instruction by comparing the instruction identifier of the operation code/data.
2) An instruction transfer control device comprising: