JPS63234328A - Processing method for interruption of computer - Google Patents

Abstract

PURPOSE:To reduce hardware in size and cost by performing the interruption processing on the inside of a CPU without providing an interruption signal holding circuit on the outside of the CPU. CONSTITUTION:An interruption signal A is supplied to an interruption pin and an input-1 pin of a CPU 4. The CPU 4 is shifted to an interruption processing routine from a main routine with input of the signal A and then inhibits the subsequent interruptions to carry out the interruption processing. When this interruption processing is over, the CPU 4 is reset to the main routine. In this case, however, an interruption inhibiting state is not released. Instead a fact that the signal A is not active is confirmed and an interruption permitted by an interruption signal sense routine that is carried out in the intervals of the normal processing in the main routine. In such a permission >=2 times interruption are prevented by the same interruption signal. As a result, an interruption signal holding circuit set on the outside of the CPU can be omitted for reduction of the hardware in size and cost.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an interrupt processing method using level detection type interrupt signal detection in a computer system.

[Conventional technology]

The conventional interrupt method of this type is transistor technology 1.
October 985 issue, volume 253 (CQ Publishing) No. 443
There is one described on pages 454 to 454. An example of a conventional interrupt signal input circuit will be described below with reference to FIG. The interrupt signal input circuit shown in the figure is composed of a flip-flop 1 for holding an interrupt signal. The flowchart of the interrupt processing is shown in FIG. 3, and the time chart is shown in FIG. 4. As shown in the figure, at the rising edge of the external interrupt signal A (Fig. 2), the output Q of flip-flop 1
is set to “11,” and CPU (Central Processing Unit) 2
An interrupt occurs. That is, the interrupt signal B is supplied to the CPU 2. When an interrupt occurs, the CPU performs various processes for the interrupt, outputs an interrupt signal reset pulse C, executes an interrupt enable instruction (EI), and ends the interrupt process.

The interrupt signal reset pulse C initializes the flip-flop 1, and then the external interrupt signal A
The interrupt signal B to the CPU is “L tp” until
will be maintained. Therefore, regardless of the length of the interrupt signal active time TA (FIG. 4), the interrupt process is executed only once each time the interrupt signal A from the outside is input.

[Problem that the invention seeks to solve]

However, the above-mentioned interrupt processing method requires an interrupt signal holding circuit to be provided outside the CPU, resulting in a problem that the hardware size is large and the cost is high.

An object of the present invention is to eliminate the above-mentioned problem that an interrupt signal holding circuit is required outside the CPU, and to provide a device with small hardware size and low cost.

[Means for solving problems]

The interrupt processing method of the present invention includes, upon receiving an interrupt signal,
From the main routine, move to a routine for interrupt processing that includes an instruction to disable subsequent interrupts, execute it, and return to the main routine when it is finished, and interrupt signal processing between the main routine's normal processing. Execute a sense routine that detects whether the interrupt signal is active, and after moving from the above interrupt processing routine to the main routine, if the sense routine detects that the interrupt signal is not active at least once, an interrupt enable instruction is executed. The above sense routine includes:
It is characterized in that it is programmed to be executed at a time interval shorter than the time interval from one interrupt signal to the next interrupt signal.

[For production]

In the above processing method, all interrupt processing is done by the CP.
This is done inside the U. That is, when an interrupt signal occurs,
Move from the main routine to the routine for interrupt processing. In the interrupt processing routine, subsequent interrupts are prohibited and the interrupt processing is performed. When this is finished, the process returns to the main routine, but at this time, interrupt prohibition is not canceled, that is, interrupts are not enabled. Instead, a sense routine executed between normal processing of the main routine confirms that the interrupt signal is no longer active, and then permits the interrupt. This is to avoid repeating interrupt processing for the same interrupt signal.

Also, the time interval before the sense routine is executed is
It is programmed to be shorter than the time interval from one interrupt signal to the next. As a result, there is no possibility of failing to detect an interrupt signal.

〔Example〕

FIG. 1 shows an interrupt signal circuit used in one embodiment of the present invention, and FIG. 5 shows a flowchart of its processing method.

As shown in FIG. 1, the interrupt signal A is input to the interrupt pin of the CPU 4 and the input 1 pin for detecting the interrupt signal, without passing through the interrupt signal reset circuit as shown in FIG. When this interrupt signal A is input, the CPU 4 shifts from the main routine to a routine for interrupt processing. In the routine for interrupt processing, as shown in FIG. 5(a), after prohibiting future interrupts (202), interrupt processing (20
Execute 4). When the interrupt processing is finished, the interrupt enable instruction is not executed and the process returns to the main routine with interrupts disabled (206>. The main routine performs the original processing a to processing C (102) as shown in FIG. 5(b). ,112,12
2), but each time each process is completed, the interrupt signal sense routine (104, 114, 124>) is executed.In the interrupt signal sense routine, after confirming that the interrupt signal A is not active, 105, 115, 125
) Execute interrupt enable instruction (106, 116, 126
).

Next, the operation will be explained using the time chart shown in FIG. When interrupt signal A becomes active (“H99”), interrupt processing is started and interrupts are disabled.
The interrupt permission in the figure becomes L''.

This is to prevent acceptance of another interrupt while one interrupt is being executed. When the interrupt processing ends, the process returns to the main routine, but interrupts continue to be disabled. The next time an interrupt is permitted is at the timings 81 to S3 in FIG. 6, that is, in the first interrupt signal sensing routine after the interrupt signal becomes inactive.

By allowing an interrupt after confirming that the interrupt signal is no longer active in this way, it is possible to prevent one interrupt signal from causing two or more interrupts.

Next, the time during which interrupt signal A is not active is TA (
TAI in Figure 6, TA2>, the time required for each process of the main routine T)l (THa-T in Figure 6) Ic)
shall be. If TA < TH, that is, the next interrupt signal occurs before the main routine processing is completed, the interrupt will not occur even though the interrupt signal A has been input, as shown in Figure 7. It happens that it does not occur. Therefore, the maximum value T Hma within the normally possible range of T)1
TH is set so that x is smaller than the normally possible minimum value TAmin of TA. In this embodiment, TH is the time for each process in the main routine. In other words, since there is a time from one interrupt signal sensing routine to the next interrupt signal sensing routine, THmax<TA
By inserting the interrupt signal sensing routine so that m1n occurs, it is possible to prevent failure to execute interrupt processing when an interrupt signal is received.

(Effects of the Invention) As described above, according to the present invention, an interrupt signal holding circuit outside the CP port is unnecessary, so that there is an effect of reducing the size of hardware and reducing costs. Furthermore, since the interrupt prohibition period is longer than in the prior art, noise resistance against the interrupt signal input line is improved. This is because while interrupts are disabled, even if noise appears on the interrupt input line, the CPU is not affected by it.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an interrupt input circuit used in an embodiment of the present invention, FIG. 2 is a block diagram showing a conventional interrupt signal input circuit, FIG. 3 is a flowchart showing conventional interrupt processing, and FIG. 4 5 is a flowchart showing interrupt processing in an embodiment of the present invention. FIG. 7 is a time chart 1 to 1 for explaining the timing of execution of a sense routine. 4...CPU, 104. ．． 114.124... Interrupt signal sense routine, 105.115.125...
Interrupt signal detection, 106, 116.126... Interrupt permission, 202... Interrupt prohibition, 204... Interrupt processing. The present invention [; depending on the input circuit one time

Claims (1)

[Claims] In an interrupt processing method using level detection type interrupt signal detection, when an interrupt signal is received, the main routine moves to a routine for interrupt processing that includes an instruction to prohibit subsequent interrupts. and return to the main routine when it is finished, and execute a sense routine that detects whether the interrupt signal is active in between the main routine's normal processing; and the above interrupt handling routine. and executing an interrupt enable instruction at least once the sense routine detects that the interrupt signal is not active; 1. A computer interrupt processing method, characterized in that the computer is programmed to be executed at a shorter time interval than the current time interval.