JPH06350677A - Interrupt request type switching request signal monitoring system - Google Patents

Abstract

PURPOSE:To report the state change of a switching request signal with an interrupt request signal again by stopping the sampling clock of the switching request signal till the reset of the interrupt request signal after the data read processing of a CPU. CONSTITUTION:When an interrupt request signal In goes to the active state, a CPU 1 outputs the address value corresponding to a register, where a switching request signal Sw is stored, and a read control signal Rc and reads in data on a data bus Da to monitor the switching request signal Sw. After the CPU 1 reads in data, a reset signal Rs is outputted from an interrupt request control part 3 to release the active state of the interrupt request signal In. A sampling control part 6 masks a clock C1 to stop the output of a sampling clock Cs till the reset of the interrupt request signal In after the CPU 1 starts the data read processing to a register part 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching request signal monitoring system, and more particularly to a switching request signal monitoring system for monitoring a switching request signal generated due to a failure of a transmission line between communication devices or a failure of a panel in the device. .

[0002]

2. Description of the Related Art In a conventional interrupt request type switching request signal monitoring system, as shown in FIG. 2, a CPU (processor) 1 for monitoring a switching request signal Sw, a switching request from an address Ad from the CPU 1 and a read control signal Re. The output permission control unit 2 for outputting the output permission signal En for permitting the value of the register storing the state of the signal Sw to be output onto the data bus Da, and the output permission signal En from the output permission control unit 2 An interrupt request control unit 3 that outputs a reset signal Rs that is input and resets the interrupt request signal In
And N (N: positive integer) switching request signals Sw are sampled by the clock Cl from the CPU 1 to detect changes in the switching request signals Sw, and the interrupt request signal In and the switching request signals are detected. A change point detection unit 4 that outputs a register control signal St for writing the state of the signal Sw to the register, and resets the interrupt request signal In when the reset signal Rs from the interrupt request control unit 3 is input; The register unit 5 stores the state of each switching request signal by the register control signal St from the unit 4, and outputs each register value to the data bus Da when the output enable signal En from the output permission control unit 2 is input. And have.

[0003]

According to this conventional interrupt request type switching request signal monitoring system, the CPU outputs a read control signal and the CPU takes in the data on the data bus until the interrupt request signal is reset. If the switching request signal changes during the period, there is a problem that the CPU cannot be notified of this state change by the interrupt request signal.

An object of the present invention is to provide an interrupt request type switching request signal monitoring system which solves such a problem.

[0005]

According to the interrupt request type switching request signal monitoring system of the present invention, an interrupt request signal is input and N is input.
(N: Positive integer) CPU that monitors the number of switching request signals
An output permission control unit for inputting an address and a read control signal from the CPU and outputting an output permission signal for permitting output on the data bus; and an output permission signal from the output permission control unit and the CPU. An interrupt request control unit for inputting the clock of the above and outputting a reset signal for resetting the interrupt request signal after the completion of the data reading process of the CPU, an output permission signal from the output permission control unit, and a clock from the CPU. A sampling control unit that outputs a sampling clock that stops sampling of the switching request signal from the data reading process of the CPU until the interrupt request signal is reset, and the switching request signal and the reset from the interrupt request control unit. Switching by inputting signal and sampling clock from the sampling control unit A change point detecting section for outputting the interrupt request signal for notifying the CPU of a change in the state of the request signal and a register control signal for writing each switching request signal state in the register, and N change point detecting sections from the change point detecting section. A register unit for inputting the register control signal for the switching request signal and the output permission signal from the output permission control unit and outputting the register value on the data bus is provided.

[0006]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. In this interrupt request type switching request signal monitoring system, N switching request signals S are input by the input of the interrupt request signal In.
CPU (processor) 1 for monitoring w and this CPU 1
An output enable signal En for inputting the address Ad from the memory and the read control signal Re to give output permission to the data bus Da.
And the output permission control unit 2 for outputting
Output enable signal En from CPU and clock Cl from CPU 1
Is input to output the reset signal Rs for resetting the interrupt request signal In after the CPU 1 completes the data reading process, the output enable signal En from the output enable control unit 2 and the clock Cl from the CPU 1. Sampling control section 6 for outputting sampling clock Cs for stopping sampling of switching request signal Sw from the data reading process of CPU 1 to resetting of interrupt request signal In, and N switching request signals Sw.
The interrupt request signal In for notifying the CPU 1 of the state change of the switching request signal Sw by inputting the reset signal Rs from the interrupt request control unit 3 and the sampling clock Cs from the sampling control unit 6 and the respective switching request signals Sw. Register control signal St for writing the state to the register
And a register unit 5 for inputting the register control signal St from the change point detector 4 and the output permission signal En from the output permission control unit 2 and outputting the register value onto the data bus Da. Composed of and.

Next, the operation of this embodiment will be described.

When the interrupt request signal In becomes active, the CPU 1 outputs the address value corresponding to the register storing the state of the switching request signal Sw and the read control signal Re to read the data on the data bus Da. Thus, each switching request signal Sw is monitored. The active state of the interrupt request signal In is released by the CPU 1 reading the data completely and then outputting the reset signal Rs from the interrupt request control unit 3.

When the CPU 1 is not performing the data reading process for the register unit 5, the sampling control unit 6 keeps the clock Cl as it is as the sampling clock Cs.
Then, the CPU 1 starts the data reading process with respect to the register unit 5 and masks the clock Cl until the interrupt request signal In is reset, thereby stopping the output of the sampling clock Cs.

The conversion point detector 4 uses the sampling clock C.
s detects each edge of the switching request signal,
When a change from 0 to 1 is detected, the register value is set to 1. Conversely, when a change from 1 to 0 is detected, a register control signal St for setting the register value to 0 is output, and at the same time, either change is made. When it is detected, the interrupt request signal In is output.

FIG. 2 shows an example of the timing at which the sampling clock Cs stops.

Point a shows the timing at which the CPU 1 takes in the data on the data bus Da, point b shows the timing at which sampling is restarted, and point c shows the timing at which the interrupt request signal In is reset.

All state changes of the switching request signal Sw from point a to point b are sampled at point b, and the interrupt request signal In reset at point c is output again at point b.

[0015]

As described above, according to the present invention, the sampling clock of the switching request signal is stopped from the data reading process of the CPU to the resetting of the interrupt request signal, thereby resetting the interrupt request signal from the data reading process of the CPU. It is effective that the state change of the switching request signal until later can be notified by the interrupt request signal again.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a timing at which a sampling clock stops.

FIG. 3 is a block diagram of a conventional interrupt request type switching request signal monitoring system.

[Explanation of symbols]

 1 CPU (processor) 2 Output permission control unit 3 Interrupt request control unit 4 Change point detection unit 5 Register unit 6 Sampling control unit Ad address Re Read control signal Cl clock En Output permission signal Rs Reset signal Cs Sampling clock Sw Switching request signal In Interrupt request signal St register control signal Da data bus

Claims (2)

[Claims] 1. A CPU for inputting an interrupt request signal to monitor N (N: positive integer) switching request signals, and an address and read control signal from this CPU for output on a data bus. An output permission control unit that outputs an output permission signal that gives permission, and an output permission signal from the output permission control unit and a clock from the CPU are input to reset the interrupt request signal after the data reading process of the CPU is completed. An interrupt request control unit for outputting a reset signal for inputting the output enable signal from the output enable control unit and a clock from the CPU, and the switching request from the data reading process of the CPU to after the interrupt request signal is reset. A sampling control unit that outputs a sampling clock that stops signal sampling; the switching request signal and the interrupt request The reset signal from the control unit and the sampling clock from the sampling control unit are input to change the state of the switching request signal by the C
A change point detecting section for outputting the interrupt request signal notified to the PU and a register control signal for writing each switching request signal state to a register, and a register control signal for N switching request signals from the change point detecting section And a register unit for inputting an output enable signal from the output enable control unit and outputting a register value on a data bus. 2. The change point detection unit detects each edge of the switching request signal by the sampling clock, and when detecting a change from 0 to 1, sets a register value to 1, and vice versa. 2. The interrupt request type switching request signal according to claim 1, wherein a register control signal for setting the register value to 0 is output when the change to the interrupt request is detected, and an interrupt request signal is output when either change is detected at the same time. Monitoring method.