JPH01306930A - Microprocessor - Google Patents

Abstract

PURPOSE:To save an accidental memory parity error, data read error from a peripheral apparatus, etc., when such abnormal state in which the accidental errors are produced occurs while an instruction is executed by copying the content of a holding register in an execution register upon receiving a retry signal. CONSTITUTION:In order to make a retry possible, the content of an execution register 1 before executing an instruction is copied in corresponding individual registers of a holding register 3 and the execution register 1 is changed by executing the instruction at the address designated by a program counter. When a retry signal 4 is not effective after execution, execution of a program is caused to proceed from a repeating point 5. when the retry signal 4 is effective, the content of the holding register 3 is returned to the execution register 1 and the program is reexecuted from the repeating point 5. Therefore, the instruction can be reexecuted and an accidental error can be saved.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to microprocessors.

[Conventional technology]

Conventional microprocessors do not have a so-called retry function for re-executing an instruction that has been executed several times depending on external input conditions.

[Problem to be solved by the invention]

As mentioned above, conventional microprocessors do not have a retry function, so when reading memory with a certain instruction, noise may occur when a parity error occurs in the read data or when accessing various peripheral devices. This has the disadvantage that when the program cannot read the results expected in advance, the program moves to an error routine or stalls.

[Means to solve the problem]

The microprocessor of the present invention has an execution register that includes various individual registers used for its operation, and a holding register that has a second individual register that is paired with the individual register to hold the state of the execution register before instruction execution. and a retry terminal for inputting a retry signal to re-execute the command.

That is, the microprocessor of the present invention has an execution register having a plurality of individual registers necessary for executing an instruction, including an accumulator, a program counter, general-purpose registers, and flags, and a pair with each of the individual registers of the execution register. It includes a holding register having a plurality of individual registers, and a retry terminal for inputting a retry signal including a memory parity error signal or a data read error signal from a noise or peripheral device controller to re-execute an instruction.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a flow diagram showing the operation of an embodiment of the present invention.

In this embodiment, the execution register (RRegi) 1 involved in the actual operation of the microprocessor includes a program counter, an accumulator, general-purpose registers, and all individual registers such as flags and segments. Note that the subscript i takes a value from 1 to the total number of registers n. For example, RRegl is the program counter and RReg2 is the accumulator.
Each has its own individual register.

The initial value (CONTi)2 is the execution register (RReg).
i) Indicates the initial value of 1, and executes after reset (RR).
The initial value (CONTi) is copied to egi)1.

Next, in order to enable re-execution (retry), the contents of execution register (RRegi) 1 before instruction execution are copied to the corresponding individual j register of holding register (HRegi) 3, and the program counter (RRegt) The instruction at the address indicated by is executed and the execution register (RReg
i) Update 1. After this execution, if the retry signal 4 is not valid, the program returns to the repeat point 5 and continues executing the program. If the retry signal 4 is valid, the holding register (HRegi) 3 is returned to the execution register (RRegi) 1, and the process returns to the repetition point 5 to perform re-execution. Here, the retry signal 4 is a memory parity error signal, noise, or a data read error signal from a peripheral device controller.

〔Effect of the invention〕

As explained above, the microprocessor of the present invention has
b) Individual registers built into the microprocessor,
Each execution register and holding register are duplicated, and the execution register from before execution of one instruction is copied to the holding register to prevent accidental memory parity errors or data from peripheral devices when executing an instruction. If an abnormal condition such as a read error occurs, the instruction can be re-executed by copying the holding register to the execution register in response to a retry signal. It has the effect of being able to provide relief.

[Brief explanation of the drawing]

FIG. 1 is a flow diagram showing the operation of one embodiment of the present invention. 1... Execution register, 2... Initial value, 3... Holding register, 4... Retry signal.

Claims (1)

[Claims] an execution register having a plurality of individual registers necessary for execution of an instruction, including an accumulator and a program counter and general purpose registers and flags, and a holding register having a plurality of individual registers paired with each of said individual registers of said execution register. and a retry terminal for inputting a retry signal including a memory parity error signal or noise or a data read error signal from a peripheral device controller in order to re-execute an instruction.