JPH0296847A - Trace controller - Google Patents

Abstract

PURPOSE:To collect history information at a high speed and to eliminate a read bus between a maintenance device and a diagnosis device by storing common bus information into trace memories at any time, switching and storing it to the other when one becomes full and transmitting the content of the memory which became full to a main storage. CONSTITUTION:The title controller contains first and second trace memories 10 and 11. When one of the trace memories 10 and 11 becomes full in the storing action of common bus information, switch control storing bus information into one of the trace memories 10 and 11 is performed. While a storing processing for one 11(10) of the trace memories is performed, the content of the other trace memory 10(11) which becomes full is write-controlled from a trace controller 1 to the main storage device. Thus, it is unnecessary to newly read the content of the trace memories 10 and 11 when the collection of history information becomes necessary. Thus, history information can be collected at a high speed and a connection line is eliminated from providing between the maintenance device and the diagnosis device.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a trace control device that collects operation history information of a common bus that connects various control devices constituting an information processing device, and particularly relates to a trace control device that collects operation history information of a common bus that connects various control devices that constitute an information processing device. Related to information read control.

[Conventional technology]

Conventionally, when it becomes necessary to collect the operation history information of the common bus stored in this type of trace control device, the information is collected from the maintenance/diagnosis device via a readout bus that is specially connected to the maintenance/diagnosis device. They received control instructions, read out and collected data.

[Problem to be solved by the invention]

The conventional trace control device described above collects the stored operation history information of the common bus and stores it from the trace control device to the maintenance/diagnosis device or from the maintenance/diagnosis device to the main storage device via the read bus. However, since it is a method, it requires a lot of time for data collection, and has the drawbacks that a read bus is required between the trace control device and the maintenance/diagnosis device.

1. Means for Solving the Problems] The configuration of the trace control device of the present invention is such that the trace control device stores the operation history of a common bus that connects various control devices constituting an information processing device. The information storage status in the first and second trace memories that store bus information and the first or second trace memory is monitored, and if the information storage is full, the trace memories are A series of steps in which a main memory write request is made to store the contents of the memory in the main memory, and upon receiving a request acceptance report, the contents of the first and second trace memories are stored in the main memory. a bus request control circuit that performs control, and first and second addresses that store write and read addresses for the first and second trace memories.
A trace monitor that monitors the operating status of the common bus and controls writing when it is determined that writing is necessary, in order to instruct writing of bus information of the common bus to the register and the first or second trace memory. a write control circuit; and a flip switch for selectively displaying which of the first or second trace memory the bus information of the common bus is to be stored.
It has a function to store the common bus information in the trace memory at any time, and when one trace memory becomes full, it switches to the other trace memory and stores it in the other trace memory. It is characterized by including a function of sending the contents of the trace memory to the main storage device.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the connection state of each control device in an information processing device including the trace control device of the present invention, and FIG. 2 is a block diagram inside the trace control device l of FIG. 1. .

In FIG. 1, l is a trace control device, 2 is an input/output control device, 3 is an arithmetic unit, 4 is a maintenance/diagnosis device, 5 is a main storage device, and each control device is connected to the system bus via OO. 1 to 4 perform successive read/write operations between the main memory device 5 and its own storage unit (not shown), and each control device 1 to 4.
4 communication control operations are executed, and these various operating conditions are stored as history information in the trace memory in the trace control device l.

In FIG. 2, lO is the first trace memory TRMA, .
11 is the second trace memory TRMB, 12 is TRM
A, 10 address registers AA, 13 is TRMB
11 is an address register AB; ]4 is a tracer write control circuit that controls writing of the system bus 100 to the tracer memory; 15 is a TRMAlo, or;
A bus request control circuit that controls writing of the contents of TRMBl 1 to the main memory 5, 18 is TRMAlo, TR, MBl
, 1 is a switching circuit MPX which selects the output of 1, 16 is 'IRM
This is a flip-flop F that indicates which bus information of the system bus 100 is written to A10 or TRMBII.

Next, how each block in the tracer device 1 operates will be explained.

When the information processing device is started up (when the power is turned on or when the system is reset), AA12, AA13, and F16 are all 0.
', and the bus request control circuit 15 and tracer write control circuit 14 are initialized.

When F16 is a logic value of 101, TRMA 10 is selected, and when F16 is a logic value of "1", TRMA10 is selected.

First, a tracer write start instruction command is issued via the system bus 100 by the control device 4 connected to the system bus 100.

The tracer write start command is notified to the tracer write control circuit 14 via the connection line 60, and since F16 has a logical value of 0°, the contents of the system bus 100 are stored in TRMAlo via the connection line 50. be done.

Operations on system bus 100 are performed using bus clock IT
In many cases, the process does not end at 1, and AA12 is incremented by +1 as the bus clock T changes, and the bus information on system bus 100 at that time is stored in TRMA10 as needed.

When AA12 is added +1 in accordance with the system bus operation, at a certain time all AA12 becomes 1'', and T
The bus information on the system bus 100 is stored in all addresses of RMAl 0.

At this time, the tracer write control circuit 14, which inputs AA12 through the connection line 54, detects that all AA12 have become 1', shifts F1.6 to the logical value "1", and system - Control the bus information on the bus 100 to be stored in TRMBII.

The write operation to TRMB 11 is performed using the TRM described above.
The operation is similar to that for A10, and AB13 is TAM
It is added by +1 in accordance with the write operation to B11,
When AB13 becomes all 1', F16 is shifted to logic value O.

On the other hand, the bus control circuit 15 also monitors AA12 and AB12 via the connection lines 55 and 56, and when it detects that AA12 has become all 1'', the bus control circuit 15 also monitors the AA12 and AB12 via the connection lines 59 to the main storage device 5. Make a write request.

Once permission to use the system bus 100 is obtained, AA,
While subtracting 12 from 11, control is performed to write the history information stored in the TRMA 10 to a predetermined address in the main storage device 5, and the operation ends when all AA12 becomes "0".

MPX18 outputs TRMAl when F16 has a logic value of '1'.
0 is selected, and TRMBll is selected when the logical value is 0°.

The operation for writing the history information stored in the TRMB 11 to the main memory bag π5 is similar to the operation for writing TRMAl 0 to the main memory device 5.

The tracer write control circuit 14 always monitors the operating status of the system bus 100, and bus operations that do not require tracing, such as write operations from the tracer control device to the main memory, are not stored in the trace memory. This control is also performed.

At this time, if an unnecessary bus operation is detected, the +1 addition of AA12 or A813 is naturally also inhibited.

When it becomes necessary to collect historical information, the historical information can be collected by reading the stored information from the trace memory in the main storage device.

〔Effect of the invention〕

As explained above, the present invention has first and second trace memories, and when one trace memory becomes full in the operation of storing common bus information, the bus is transferred to the other trace memory. Performs switching control for storing information, and while data is being stored in one trace memory, the trace control device writes the contents of the other trace memory to the main memory when it becomes full. By doing so, there is no need to read the contents of the trace memory anew when it is necessary to collect historical information, so historical information can be collected at high speed, and there is no need to read out the contents of the trace memory when it is necessary to collect historical information. This has the effect that there is no need to provide a connection line.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing connections between a trace control device and each control circuit constituting an information processing device according to an embodiment of the present invention;
FIG. 2 is a block diagram inside the tracer control device of FIG. 1. 1... Trace control device, 2... Input/output control device,
3... Arithmetic device, 4... Maintenance/diagnosis device, 5...
Main memory, 10.11...Trace memory, 12
13...Counter, 14. ．． 15...control circuit, 1
6...Flip-flop, 7...Selection circuit, 0...System bus.

Claims (1)

[Claims] In a trace control device that stores the operation history of a common bus that connects various control devices constituting an information processing device, first and second trace memories that store bus information of the common bus; , monitors the information storage status in the second trace memory, and when the information storage becomes full, makes a main memory write request to store the contents of those trace memories to the main memory, and , upon receiving the request acceptance report, the first and second traces are processed.
a bus request control circuit that performs a series of controls for storing the contents of the memory in the main memory; and the first and second trace controllers.
first and second address registers for storing write/read addresses to and from the memory, and the common bus for instructing writing of bus information of the common bus to the first or second trace memory. A trace write control circuit that monitors the operating status of the bus and performs write control when it is determined that writing is necessary, and selects and displays whether to store the bus information of the common bus in the first or second trace memory. It has a function to store the common bus information in the trace memory at any time, and when one trace memory becomes full, it switches to the other trace memory and stores it in the other trace memory. A trace control device comprising a function of transmitting the contents of the trace memory to the main storage device.