JPS6129953A - Trace controlling method - Google Patents

Abstract

PURPOSE:To obtain extremely various mode tracing function by setting a write enable signal and trace additional information on a write-register by a processor and performing write-action onto a memory device of the processor itself. CONSTITUTION:When the processor of a channel device 100 permits write-action a trace mode RAM write-register to write trace mode information to be set a write enable signal 205 turns on. In such a condition, when the processor reads out a region of its own memory device on which the processor is intending to operate tracing and writes read-out data in the region as they are, the address in the region outputs to an address bus 110. Further, a light signal line 112 of a debug console interface bus 101 turns on, so that the result is input in an AND circuit 206 together with the write enable signal 205 to turn on a write signal of a trace mode RAM201, and the trace mode information preliminarily set on a register 202 is written in a RAM201.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a trace control system, and more particularly to a trace control system in a trace device of a data transmission channel device controlled by a microprocessor, for example.

(b) Conventional technology Fault analysis or operation check on data transmission paths is generally performed by tracing transmitted characters. And for that purpose, online scopes etc. are provided. However, online scopes and the like generally only trace transmission signals between a channel and a modem, and cannot trace the operating status of a channel device.

(c) Problems to be Solved by the Invention Therefore, it is effective to provide a channel device with a tracing function for transmission characters, etc., but a sufficient tracing function requires a large memory capacity and tracing processing by channel control firmware. However, this method is difficult to implement because it increases costs and reduces channel device throughput.

(d) Means for Solving the Problems In order to solve the above problems, the present invention incorporates a processor and a storage device of the processor itself, and a data signal line connected to the processor.

In a tracing device for a processing device having a debugging console interface constituted by an address signal line and a bus control signal line, a first storage device that is assigned the same address as the storage device of the processor itself and stores additional information of the trace operation. and a second storage device that sequentially stores the address signal or data signal on the dehunk console ink interface and a part of the trace additional information based on the trace additional information outputted by the first storage device; A write register to the first storage device is provided, the write register being writable by the processor, and the processor sends a write permission signal to the write register to the first storage device, By setting trace additional information to be stored and performing a write operation to the memory device of the processor itself, the trace additional information set in the write register is written to the same address area of the first memory device, and the trace information is stored. The present invention is characterized in that the tracing operation is controlled based on additional information.

(e) Operation The present invention utilizes a debug console interface that is normally provided in a channel device of a microprocessor control unit, connects a trace device to the debug console interface, and traces various modes such as address signals and data signals. The trace function is realized without affecting the operational firmware, etc.

(F) Embodiment FIG. 1 is a block diagram of a tracing device according to an embodiment of the present invention. In the figure, 100 indicates a data transmission channel device,
1 is a debug console interface bus, 110 is an address bus, 111 is a data bus, 112 is a debug console interface write signal line, 200 is a trace device, 201 is a trace mode RAM, 202 is a trace mode RAM write data register, 203 is a trace addition Information signal line 2204 is a trace control information signal line, 205 is a trace mode RAM write permission signal line,
206 is an AND circuit, 210 is a trace RAM, 21
1 is a trace RAM address counter, 212 is a trace information selection circuit, 213 is a trace RAM write signal line, 214 is a trace RAM address count up signal line, 215 is a trace information selection signal line, 2 and 20 are trace control unit II, 240 is the debug console interface driver/receiver circuit.

The trace device 200 includes a data transmission channel device 2100
The debug console interface bus 101 is connected to the debug console interface bus 101. The trace mode RAM 201 is connected to the microprocessor's address bus 110, and has a one-to-one correspondence with the microprocessor's own storage device.

That is, when the microprocessor performs a read/write operation on a certain memory area or an instruction fetch operation, trace control information and trace additional information corresponding to that memory area are output from the trace mode RAM 201. When this trace control information matches the trace condition, the contents of the data bus IIl or address bus 110 of the microprocessor sensor are transferred to the trace information selection circuit 212.
Trace R is selected in conjunction with trace additional information 203.
Written to AM210.

After this, the trace RAM address counter 211 increases by +1.
and indicates the write address of the next trace information. This trace RAM address counter 211 can perform various operations depending on the trigger mode, such as starting or stopping the count amplifier by a trigger, and stopping after counting a certain number of times from the trigger, but this is generally not done in a trace device. Since this is a controlled control, the explanation will be omitted.

Further, the trace control circuit 220 has a trace mode RAM.
The write signal 213. of the trace RAM 210 is generated by the trace control signal 204 from the trace RAM 20/ and a trace instruction by a switch of a trace device (not shown). ) An address count up signal 214 for the race RAM address counter 211, a trace information selection signal 215, etc. are generated. Next, the trace mode RAM 20 shown in FIG.
The trace operation will be explained based on the output data example of No. 1.

The "send/receive command" in the additional trace information indicates that the trace information is a command issued by software to the channel device, and the "send/receive status" indicates that the trace information is command completion information. “
``Sent/Received Characters'' indicates that the trace information is the character that the channel device attempted to send or received. By storing these trace additional information in the area of the trace mode RAM 201 corresponding to the area, for example, the trace mode RAM 201 can be stored at the timing when the microprocessor writes the transmission data to the transmission data temporary storage area.
The additional trace information of the transmission character (0011) is output and written to the trace RAM 210 together with the transmission data on the data bus 111.

Further, the trace additional information "instructions θ to 7" enables specifying the start addresses of eight arbitrary instructions in the control program of the microprocessor and tracing them as checkpoints of the operation of the microprocessor.

That is, when a microprocessor fetches an instruction at a certain address, for example, trace mode RAM2-
Instruction 1 (10) of trace additional information in the area corresponding to 01
01) is stored, the trace mode RAM 20
1 outputs trace control information instruction 1 (10, 01), and the execution of instruction 1 by the microprocessor is recorded in the trace RAM 210.

As is clear from the above explanation, the additional information of the trace mode and the trace mode can all be defined arbitrarily by the user, and although an example of 4 bits of additional information has been shown, increasing these bits is also possible in the trace mode RAM 201. It is sufficient to increase the bit width of the trace RAM 210, which is highly flexible.

Next, the trace control information shown in FIG. 2 will be explained.

"No trace" (000) indicates that the data or address that the microprocessor is reading/writing is not related to the trace operation. “Data trace” (0
1X) indicates that the data on the data bus 110 is to be stored as trace information.

"'Address trace 1.2" (10x, 1lx)
instructs to store a portion of the address on the address bus 110 as trace information. This is used to determine whether or not to perform a trace operation based on the type of transmitted character.

Generally, in a microprocessor-controlled data transmission channel device, a character check table as shown in FIG. 3 is used to check transmission characters in order to improve processing speed.

Here, an example of the use of the received character check table shown in FIG. 3 will be briefly described. The received character check table has received character codes (00), ... (FF)1. This is a table that stores the start address of the processing program corresponding to , and the processing is performed in the following steps.

(a) Set the upper byte (X, X2) of the table start address in the upper byte of the X register. (The lower byte of the start address is (00), □.) (bl
The code of the received character (, Y
, Y2).

fc) Read the address indicated by the X register and store it in the Y register. (The lower hide of the address of this read operation indicates the received character code.) (dl Branch to the address indicated by the Y register.

Now, the received character code "S" is stored in the area of the trace mode RAM 201 corresponding to this received character check table.
By setting "address trace 1" in the area corresponding to transmission control characters such as "TX" and "address trace 2" in the area corresponding to characters used in normal message data, the microprocessor “Address trace 1, 2” every time indexes the received character check table
The instruction is output from the trace mode RAM 201, and the character code section of the address bus 110 is output from the trace mode RAM 210.
written to.

At this time, if an instruction is given to the trace control circuit 220 to trace only 'address trace 1',
Only transmission control characters can be traced. Furthermore, for characters other than transmission control characters, it is easily possible to trace only a predetermined number of characters following the transmission control characters.

Finally, a method of setting trace mode information in trace mode RAM 201 will be explained.

The trace mode RAM 201 is in normal read mode,
The contents of the area specified by the address bus 110 are output. The trace mode information is sent as follows. The channel device microprocessor writes the trace mode RAM write register 202 to the trace mode RAM write register 202.
M write permission and write trace mode information to be sent. As a result, the trace mode RAM write permission signal line 205 is turned on. In this state, if the microprocessor reads a certain area of its own storage device where it wants to perform a trace operation, and then writes continuous data to that area as it is, the address of that area will be
10, and the write signal line 112 of the bus control signal line of the debug console interface bus 101 is turned on. This write signal and the aforementioned trace mode R
The AM write permission signal is input to the AND circuit 206,
Turn on the trace mode RAM write signal. As described above, the trace mode information previously set in the trace mode RAM write register 202 is written to the trace mode VRAM 201.

At power-on, trace mode RAM write register 2
If 02 is initially set to all "OR" with the trace mode RAM write enabled, the microprocessor's initial clear operation (writing all "0" to the microprocessor's own storage device) will
The trace mode RAM is also cleared to "0".

Although not shown in FIG. 1, if a ROM storing a program for transferring various trace mode information to the trace mode RAM 201 is connected to the address bus 110 and data bus 111, the microprocessor of the channel device can store the program. By running the program,
Various trace modes can be easily set.

(G) Effects of the Invention As is clear from the above explanation, this tracing device realizes a wide variety of tracing functions without affecting actual operation, such as sending and receiving characters.

It is effective for analyzing the operation of data transmission channel devices, etc., because transmitted/received commands, command completion information, various checkpoints of microprogram processing, etc. are traced together.

Although the above embodiment shows an example of the trace operation for the data transmission channel device, it is clear that the present invention is not limited to this.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a tracing device according to an embodiment of the present invention, FIG. 2 is a diagram showing an example of output data of the trace mode RAM, and FIG. 3 is a diagram showing an example of how a received character check table is used. be. In FIG. 1, 100 is a data transmission channel device;
01 is a debug console interface bus, 110
1 is an address bus, 111 is a data bus, 200 is a trace device, 201 is a trace mode RAM, 202 is a trace mode RAM write data register, and 210 is a trace RAM.

Claims (1)

[Claims] In a trace device for a processing device that includes a processor and a storage device of the processor itself, and has a debug console interface configured of a data signal line, an address signal line, and a bus control signal line connected to the processor, the processor itself a first storage device that is assigned the same address as the storage device and stores additional information of the trace operation; and an address signal or data on the debug console interface based on the additional trace information output by the first storage device. a second storage device that sequentially stores signals and part of the trace additional information; and a write register that is a write register to the first storage device and is writable by the processor, and the processor By setting a write enable signal for the first storage device and trace additional information to be stored in the first storage device in the write register, and performing a write operation to the storage device of the processor itself, the first A trace control system characterized in that the additional trace information set in the write register is written in the same address area of a storage device, and the trace operation is controlled based on the additional trace information.