JPS58125154A - State hysteresis storing system - Google Patents

Abstract

PURPOSE:To obtain a device which facilitates the investigation of the cause of a fault due specially to a stall by providing two systems of state hysteresis storage devices capable of storing state information in different operation modes simultaneously. CONSTITUTION:The two systems of state hysteresis storage devices capable of storing the state information in different operation modes simultaneously are provided. For example, the logical operating device 2 of an information processor 1 sends out state information 20, write controlling information 22, and operation mode indication information 23; the state information 20 is held in a memory register 3 and the write controlling information 22 is held in the 1st and the 2nd memory controllers 6 and 11. Then, the operation mode indication information 23 is inputted to the 1st and the 2nd mode registers 5 and 10 to set pieces of updated condition information 24 and 25, and the state information 21 read out of the memory register 3 is inputted to the 1st and the 2nd memory devices 4 and 9. When an address of the 1st memory device 4 is specified by the address information 27, the state information 21 is written in the specified address.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a state history storage method in an information processing device, and more specifically, a method for storing state information for searching for abnormalities or failures in the information processing device, tracing operations, etc. This invention relates to a state history storage method for operating modes.

In the conventional state history storage device, state information and microprogram addresses inside the four devices are constantly traced and stored when the information processing device is operating normally. Therefore, when a complex failure occurs, the initial state is determined from the vast amount of stored state information. Furthermore, the timing for tracing and reading the status information was determined when a failure occurred and the pressure was released.

In addition, for failure detection, we used trace operations to reproduce the data for tracing the cause of the failure.

Furthermore, in the conventional system, the write timing for storing state information is generated by the memory control device for each external input signal, such as every time, every fixed period of time, every command, and every event. Therefore, since only one type of write timing signal can be selected and specified, if some abnormality or failure occurs, or if the program loops and stalls due to K such as misfilling of Ml, a stall (loop ) Only the state information and microprogram addresses inside the information processing device that are running are traced. Therefore, there was a drawback in that stalls (loops) occurred and the microphones used to investigate the cause of the situation were lost.

In other words, in addition to an arithmetic logic unit and a memory register, a conventional state history storage device includes a control unit for printing, a memory device, a combination of an address register and an adder, and so on. The required status information was stored in the memory device. Therefore, there is a limit to how much valid status information can be stored.

The purpose of the present invention is to eliminate the above-mentioned drawbacks in conventional state history storage devices, and to be able to store state information in different operating modes simultaneously! It is an object of the present invention to provide a state history storage method that makes it easy to find the cause of a failure particularly caused by a loop by utilizing a system state history storage method.

A rounding device implementing the state history storage scheme according to the invention includes an arithmetic logic unit, a memory register, first and second mode registers, first and second memory controllers, first and second memory devices, and a first and second memory controller. It consists of first and second write address registers and first and second adders. The first mode register, first memory controller, tenth memory controller, first write address register, and first adder constitute a set of state history storage portions. A second address register, a second memory controller, a second memory device, a second write address register, and a second adder constitute another set of state history storage portions. In the state history storage system according to the present invention, the two sets of state history storage device parts can be operated simultaneously in different modes.

The state information sent from the arithmetic logic unit to the memory register and held in the memory register is simultaneously transmitted to the first and second
memory device.

Since the first and second mode registers can be set to different modes, the state information is stored in the two sets of WA history storage units in different modes. The operation modes of the storage device include memory for each clock, memory for a fixed time interval, memory for each instruction, memory for each event, memory for each time a signal is input from the outside, and the first and second mode registers. defines one of the above modes independently. The first and second memory control devices generate write instruction information according to the operation mode designation information set in the first and second mode registers, respectively. According to the write instruction information, the information being added from the memory register to the first and second memory devices, respectively, is transferred to the first and second memory devices, respectively.
independently written to the Mail-11J device. Since the first and second mode registers are operating simultaneously, the above
The state history storage portions of the set are operating independently and simultaneously.

Therefore, the state information is sequentially stored in the first and 20th locking devices in nine different modes.

If a program is stalled due to an abnormality, failure, or logic failure in the information processing device, the self-development of the first and second memory devices can be traced depending on the purpose. This allows the cause of the failure to be investigated efficiently and easily.

Next, the system of the present invention will be explained in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a state history storage device that sequentially stores state history inside an information processing apparatus that implements a state history storage method according to the present invention.

In the figure, an information processing device 1 includes an arithmetic logic device, a memory register 3. First memory device 4. A first mode register 5, a first memory control device 6, a first adder 7. 1st
write address register 8, second memory device 9. second mode register 10, second memory control device 11.
It includes a state history storage consisting of a second adder 12 and a second write address register 13.

The arithmetic logic unit 2 stores status information 20, write control information 22 .
and operation mode instruction information 23.

The shape information 20 is input to the memory register 3 and is held in the memory register 3. Write control information 22 companies first
and a second memory controller 6.11. The operation mode instruction information 23 is stored in the first and second registers 5. IOK added. First and second mode registers! 1. For IOK, memory update conditions are independently set as update condition information 24 and 25, respectively. Depending on the message update conditions, status information is stored for each block, every fixed time interval, every start of command execution, every time an event occurs, or every time a signal is input from the outside.

The state information 21 read from the memory register 3 is the first.
and is input to the second memory device 4.9. Writing instruction information! 8 gives write permission and address information 2 specifies the address address of the first memory device 4, state information 2 is stored at the specified address of the 10th memory device 4.
1 is written. Similarly, write instruction information 31 provides write permission, and address information 30 provides write permission to the second memory device 9.
When the address address is specified, the status information 21 is written to the specified address of the second memory device 9.

Write control information 22 and update condition information 24 are input to the first lock control device 6 . The update condition information 24 is output according to the memory update condition set in the first mode register.

The first memory control device 6 generates write instruction information 28 based on the input information. Similarly, write control information 22 and update condition information 25 are input to the second lock control device 11 . Update condition information 25Fi is output according to the memory update condition set in the second mode register.

The second memory control device 11 generates write instruction information 31 based on the input information.

The write instruction information 28 is stored in the first write address register 8
It is also input to the first write address register 8 and gives output permission to the first write address register 8. The output of the first write address register 8 is input to the first memory device 4 as address information 27.

It is also applied to the input terminal of the first adder 7. The output of the first adder 7 is sent to the first write address register 8.
Although it is set as address information 26, address information 2
The value is incremented by +1 every time 7 is output. This specifies the address of the first memory device 4 to be written next.

Similarly, the write instruction information 31 is also input to the eighth write address register 13, and gives output permission to the second write address register 13. The output of the second write address register 13 is input as the second memory device sIK address information 30, and is also input to the second adder l! can also be added to the input terminal of The output of the second adder 12 is set in the second write address register 13 as address information 29, but every time address information 30 is output, +
The value is incremented by one. This k specifies the address of the second memory device 9 to be written next.

In this device, there is a first memory device 4, a first mode register! ! I, 3911 memory controller 6, first adder 7. and a first write address register 9.1 state history storage device portion, and an 8th memory device 9.9. Eighth mode register 1G, second memory control device 11, second adder 12. Another state consisting of the write address register 13 and the second write address register 13! 1 history storage portion can be operated independently in different modes. This is a feature of the present invention.

Here, the first and second mode registers S.

An example of an operation will be described in which different values of memory update conditions are set in 10 and different operation modes are designated by K.

Operation mode designation information 23 sent from the arithmetic logic unit 2
#c Therefore, the mode register 5 of the first controller is set to the clock-by-clock memory update mode, and the second motor register IO is set to the clock-by-clock memory update mode.
Assume that the memory update mode is set to every start of instruction execution. When the clock-by-clock memory update mode is set in the first mode register 5, the memory control device 6 of tal selects a clock signal from the write control information 22, and the write to the memory device 4 is interrupted for some reason. Unless prohibited by υ, the clock signal is output as write instruction information 28.

The logical value of the information 28 becomes IK, and the status information output from the memory register 3 at this time! l is written to the specified address of the first memory device 4.

At the time of input, the contents of the first write address register 8 are read and the address information 2 of the memory device 4 of 11111 is read.
It is used as 7. The address information 27 is added by 4 to the first adder 7, where the value of the address address is incremented by +1. The incremented value is held in the first write address register s_c. In this way, the contents of the first memory device 4 are updated by writing for each tarok, and all the state information for each operation sequence of the microprogram is stored. On the other hand, the memory is updated every time the second mode register IOK command is started. When the mode is set to 9, a signal whose logical value is IK is selected from the write control information 22 by the second lock control value -11 each time execution of an instruction is started. Therefore, unless writing to the memory device is prohibited for some reason, the corresponding signal is output as the write instruction information 31. That is, the logical value of the write instruction information 31 becomes 1 in synchronization with this signal, and the status information 21 outputted from the memory register 3b at this time is transferred to the second memory device 9.
is written to the specified address. At this time, the contents of the second write address register 13 are read and t$
The stone is used as address information 30 of the memory device 9 of 2.

Address information 30 is added by 4 to a second addition 912 where the value of the address address is incremented by +1.

The incremented value is held in the second write address register 13. In this way, every time an instruction is executed, writing is performed to update the contents of the second image processing device 9, and all the status information 21 for each instruction execution is stored.

In this way, there is a mode register S for different modes.

If 1O1ft is set, the state information 21 can be written to the first and second memory devices 4.9 simultaneously under different write update conditions.

During the period when this device is used to execute a common routine, that is, a general-purpose routine that can be used in any instruction,
- Suppose that a problem occurs. In this case, it is difficult to independently set the contents of the eight program registers so that the stall address can be stored in one mode and the instruction execution start address can be stored in the other mode. Therefore, it is possible to obtain key information for investigating stalled routines, executed commands, anomalies and failures. This makes it possible to obtain information regarding the history of the stall, which has been extremely difficult in the past. In addition, even if a fault is executed by a combination of multiple instructions, the combination of instructions is retained in one state history storage unit, making it easy to track down the cause of the abnormality or failure. . In addition to the above-mentioned memory update conditions, memory update conditions generated by information from firmware, a maintenance self-diagnosis device, or other control panel can also be set in each memory register.

As described above, according to the present invention, a system is realized in which two systems of state history storage device parts, which can be independently set to different modes, can be operated simultaneously and in parallel. This has the effect of allowing us to investigate the cause of stall (loop) failures in a very precise manner.

[Brief explanation of drawings]

FIG. 1 is a block diagram illustrating an embodiment of an apparatus for implementing the state history storage method according to the present invention. ! ... Information processing device 2 ... Arithmetic logic device 3 ...
・Memory register 4.9... Memori device 5.10
...Mode register 6.11...Memory control device 7.12...Adder 8.13...Write address registers 20 to 31...
・Information patent applicant Hisashi Inoro, agent for NEC Corporation, patent attorney

Claims (1)

[Claims] an arithmetic logic unit that sends state information, operating mode designation information, and write control information; a memory register that holds the state information; and a first device that determines a storage mode of the state information in accordance with the operating mode designation information. and a second mode register, a first mode register that instructs writing by combining the write control information and the output information of the first mode register.
a memory control device 'i42 which instructs writing based on the write control information and the output information of the second mode register; ! a first memory device into which the contents of the memory register are written, a second memory device into which the contents of the memory register are written in response to a write instruction from the second memory control device, and a first memory device into which the contents of the memory register are written. a combination of a first write address register and a first adder that provides address information; and a combination of a second write address register and a second adder that provides address information to the second memory device. , different operating modes can be set in the first mode register and the second mode register, whereby different operating modes can be set in the first mode register and the second memory device. A state history storage system configured to store the state information in an operating mode and to trace the contents of both memory devices simultaneously in different operating modes.