JP5183893B2 - 配線基板及びその製造方法、及び半導体装置 - Google Patents
配線基板及びその製造方法、及び半導体装置 Download PDFInfo
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- JP5183893B2 JP5183893B2 JP2006209845A JP2006209845A JP5183893B2 JP 5183893 B2 JP5183893 B2 JP 5183893B2 JP 2006209845 A JP2006209845 A JP 2006209845A JP 2006209845 A JP2006209845 A JP 2006209845A JP 5183893 B2 JP5183893 B2 JP 5183893B2
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- connection terminal
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- 239000004065 semiconductor Substances 0.000 title claims description 67
- 238000004519 manufacturing process Methods 0.000 title claims description 33
- 239000002184 metal Substances 0.000 claims description 56
- 239000011347 resin Substances 0.000 claims description 34
- 229920005989 resin Polymers 0.000 claims description 34
- 239000000758 substrate Substances 0.000 claims description 23
- 238000000034 method Methods 0.000 claims description 13
- 238000010030 laminating Methods 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims 2
- 230000007261 regionalization Effects 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 description 26
- 238000007747 plating Methods 0.000 description 9
- 229920001187 thermosetting polymer Polymers 0.000 description 9
- 230000004048 modification Effects 0.000 description 7
- 238000012986 modification Methods 0.000 description 7
- 238000005530 etching Methods 0.000 description 6
- 238000001039 wet etching Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 239000012779 reinforcing material Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Geometry (AREA)
- Ceramic Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
図3は、本発明の第1の実施の形態に係る半導体装置の平面図である。
図25は、本発明の第2の実施の形態に係る配線基板の断面図であり、図26は、本発明の第2の実施の形態に係る配線基板の平面図である。
11,60 配線基板
12 半導体チップ
14,21,27,61,68 絶縁層
14A,21A,27A,46A,69A〜69C 開口部
14B,14C,15A,21B,21C,27B,61A,61B,62A,64A,66A, 面
15,62 接続端子
16 配線パターン
17 配線部
18,25 ビア接続部
24,31 ビア
25 ビア接続部
31 はんだ
32,64,66 外部接続端子
34 ソルダーレジスト
36 電極パッド
37 スタッドバンプ
38 はんだ
39 アンダーフィル樹脂
43 金属板
43A 上面
45 シード層
46 レジスト膜
47 めっき膜
51 金属層
63,65 配線
76,77 はんだボール
L1〜L3 長さ
M1〜M5 厚さ
R1〜R3 直径
W1,W3,W4 幅
W2,W5 配設間隔
Claims (13)
- 第1の主面と、前記第1の主面とは反対側に位置する第2の主面と、を備えた第1の絶縁層と、
前記第1の絶縁層に設けられた開口部と、
前記第1の主面から露出する露出部を有するように前記開口部に設けられた接続端子と、
前記第2の主面に設けられ、前記接続端子と電気的に接続された配線パターンと、
前記第2の主面に設けられた第2の絶縁層と、
前記接続端子から離間した状態で前記第2の絶縁層に設けられ、前記配線パターンを介して前記接続端子と電気的に接続されたビアと、を有し、
前記接続端子及び配線パターンは、前記露出部から前記開口部内を経由して前記第2の主面上に延出するよう、一体に形成されており、
前記接続端子は、前記開口部の一部に形成され、
前記開口部内の前記接続端子が形成されていない部分には、前記第2の絶縁層が充填され、
前記開口部内に充填された前記第2の絶縁層は、前記第1の主面に露出していることを特徴とする配線基板。 - 前記接続端子及び配線パターンは、前記露出部から前記開口部の壁面を経由して前記第2の主面上に延出する一体に形成された導体層を含むことを特徴とする請求項1記載の配線基板。
- 前記配線パターンは、前記接続端子の幅よりも幅広形状とされたビア接続部を有することを特徴とする請求項1又は2記載の配線基板。
- 前記開口部には、複数の前記接続端子が所定の間隔で配設されていることを特徴とする請求項1ないし3のうち、いずれか一項記載の配線基板。
- 前記開口部は細長状に形成され、複数の前記接続端子の各々の対向する2辺は、平面視において、前記開口部の長手方向の対向する2辺に接している請求項4記載の配線基板。
- 前記露出部は、前記第1の絶縁層の前記第1の主面と略面一であることを特徴とする請求項1ないし5のうち、いずれか一項記載の配線基板。
- 前記第1の絶縁層及び前記第2の絶縁層は樹脂からなることを特徴とする請求項1ないし6のうち、いずれか一項記載の配線基板。
- 請求項1ないし7のうち、いずれか一項記載の配線基板と、
前記接続端子にフリップチップ接続された半導体チップと、
前記半導体チップと前記配線基板との間に設けられたアンダーフィル樹脂と、を有することを特徴とする半導体装置。 - 支持基板となる金属板上に、前記金属板と接する第1の主面と、前記第1の主面とは反対側に位置する第2の主面と、を備えた第1の絶縁層を形成する第1の絶縁層形成工程と、
前記第1の絶縁層に、前記金属板の上面を露出する開口部を形成する開口部形成工程と、
前記開口部に前記接続端子を形成する接続端子形成工程と、
前記第2の主面に前記接続端子と電気的に接続する配線パターンを形成する配線パターン形成工程と、
前記第2の主面に第2の絶縁層を積層する第2の絶縁層積層工程と、
前記接続端子から離間した状態で前記第2の絶縁層にビアを形成し、前記ビアを前記配線パターンを介して前記接続端子と電気的に接続するビア形成工程と、
前記金属板を除去する金属板除去工程と、を有し、
前記接続端子及び配線パターンは、前記第1の主面から露出する露出部から前記開口部内を経由して前記第2の主面上に延出するよう、一体に形成され、
前記接続端子形成工程では、前記開口部の一部に前記接続端子を形成し、
前記第2の絶縁層積層工程では、前記開口部内の前記接続端子が形成されていない部分に前記第2の絶縁層が充填され、
前記開口部内に充填された前記第2の絶縁層は、前記第1の主面に露出することを特徴とする配線基板の製造方法。 - 前記接続端子形成工程及び前記配線パターン形成工程は、前記開口部内に露出する前記金属板の上面に形成されると共に、前記開口部の壁面を経由して前記第2の主面上に延出する一体に形成された導体層を形成する工程を含む請求項9記載の配線基板の製造方法。
- 前記開口部形成工程では、複数の前記接続端子が所定の間隔で配設できるように前記開口部を形成することを特徴とする請求項9又は10記載の配線基板の製造方法。
- 前記開口部形成工程では、前記開口部を細長状に形成し、
前記接続端子形成工程では、複数の前記接続端子の各々の対向する2辺が、平面視において、前記開口部の長手方向の対向する2辺に接するように前記接続端子を形成することを特徴とする請求項11記載の配線基板の製造方法。 - 前記第1の絶縁層及び前記第2の絶縁層は樹脂からなることを特徴とする請求項9ないし12のうち、いずれか一項記載の配線基板の製造方法。
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KR1020070075463A KR101349725B1 (ko) | 2006-08-01 | 2007-07-27 | 배선 기판 및 그 제조 방법과, 반도체 장치 |
US11/882,198 US7943863B2 (en) | 2006-08-01 | 2007-07-31 | Wiring substrate and manufacturing method thereof, and semiconductor device |
EP07113606A EP1884995A3 (en) | 2006-08-01 | 2007-08-01 | Wiring substrate and manufacturing method thereof, and semiconductor device |
CNA2007101296597A CN101222818A (zh) | 2006-08-01 | 2007-08-01 | 配线基板及其制造方法以及半导体器件 |
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