JP4840305B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP4840305B2 JP4840305B2 JP2007238774A JP2007238774A JP4840305B2 JP 4840305 B2 JP4840305 B2 JP 4840305B2 JP 2007238774 A JP2007238774 A JP 2007238774A JP 2007238774 A JP2007238774 A JP 2007238774A JP 4840305 B2 JP4840305 B2 JP 4840305B2
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- lead
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
凹凸状の上面と、平坦な下面を備えた領域を複数有する板状体からなり、
この板状体の複数の領域のそれぞれは、
複数のパッド電極を備えた第1の半導体チップを搭載するための肉厚の第1の部分と、
この第1の部分の外側に上記第1の半導体チップのパッド電極に対応して配置された各々の外部電極部を構成するために設けられた複数の第1の肉厚部と、
複数のパッド電極を備えた第2の半導体チップを搭載するための肉薄の第2の部分と、
この第2の部分の外側に上記第2の半導体チップのパッド電極に対応して配置された各々の外部電極部を構成するために設けられた複数の第2の肉厚部と、
この複数の第1の肉厚部および複数の第2の肉厚部のそれぞれを囲繞するように設けられた肉薄部とを備えてなるリードフレームを用い、
上記第1の部分に搭載した上記第1の半導体チップの複数のパッド電極と、上記複数の第1の肉厚部との間を第1の接続手段で電気的に接続し、
さらに上記第2の部分に搭載した上記第2の半導体チップの複数のパッド電極と、上記複数の第2の肉厚部との間を第2の接続手段で電気的に接続した後、
上記第1および第2の半導体チップ、上記複数の第1の肉厚部の上面、上記複数の第2の肉厚部の上面、上記肉薄部の上面、および上記接続手段を、封止樹脂層により一体に封止し、
上記肉薄部及び上記肉薄の第2の部分をエッチングで除去することにより、上記複数の第1の肉厚部を外部への接続部位を構成する外部電極部として互いに電気的に分離し、上記複数の第2の肉厚部を、外部への接続部位を構成する外部電極部として互いに電気的に分離することを特徴とするものである。
図1(a)は半導体装置の構成を示す断面図、図1(b)は図1(a)の底面図である。図2(a)は単列に配置されたこの実施の形態1の配線基材として用いられるリードフレームの平面図、図2(b)は図2(a)における矢視IIb−IIb線から見た断面図、図2(c)は図2(a)における矢視IIc−IIc線から見た断面図である。
図8(a)はこの発明の実施の形態2の半導体装置の構成を示す断面図、図8(b)は図8(a)の底面図である。図9(a)はこの実施の形態2の配線基材として用いられるリードフレームの平面図、図9(b)は図9(a)における矢視IXb-IXb線から見た断面図、図9(c)は図9(a)における矢視IXc-IXc線から見た断面図である。
Claims (1)
- 凹凸状の上面と、平坦な下面を備えた領域を複数有する板状体からなり、
この板状体の複数の領域のそれぞれは、
複数のパッド電極を備えた第1の半導体チップを搭載するための肉厚の第1の部分と、
この第1の部分の外側に上記第1の半導体チップのパッド電極に対応して配置された各々の外部電極部を構成するために設けられた複数の第1の肉厚部と、
複数のパッド電極を備えた第2の半導体チップを搭載するための肉薄の第2の部分と、
この第2の部分の外側に上記第2の半導体チップのパッド電極に対応して配置された各々の外部電極部を構成するために設けられた複数の第2の肉厚部と、
この複数の第1の肉厚部および複数の第2の肉厚部のそれぞれを囲繞するように設けられた肉薄部とを備えてなるリードフレームを用い、
上記第1の部分に搭載した上記第1の半導体チップの複数のパッド電極と、上記複数の第1の肉厚部との間を第1の接続手段で電気的に接続し、
さらに上記第2の部分に搭載した上記第2の半導体チップの複数のパッド電極と、上記複数の第2の肉厚部との間を第2の接続手段で電気的に接続した後、
上記第1および第2の半導体チップ、上記複数の第1の肉厚部の上面、上記複数の第2の肉厚部の上面、上記肉薄部の上面、および上記接続手段を、封止樹脂層により一体に封止し、
上記肉薄部及び上記肉薄の第2の部分をエッチングで除去することにより、上記複数の第1の肉厚部を外部への接続部位を構成する外部電極部として互いに電気的に分離し、上記複数の第2の肉厚部を、外部への接続部位を構成する外部電極部として互いに電気的に分離することを特徴とする半導体装置の製造方法。
Priority Applications (1)
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JP2007238774A JP4840305B2 (ja) | 2007-09-14 | 2007-09-14 | 半導体装置の製造方法 |
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JP2007238774A JP4840305B2 (ja) | 2007-09-14 | 2007-09-14 | 半導体装置の製造方法 |
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JP25130799A Division JP2001077232A (ja) | 1999-09-06 | 1999-09-06 | 半導体装置およびその製造方法 |
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JP2008028414A JP2008028414A (ja) | 2008-02-07 |
JP4840305B2 true JP4840305B2 (ja) | 2011-12-21 |
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JP2007238774A Expired - Fee Related JP4840305B2 (ja) | 2007-09-14 | 2007-09-14 | 半導体装置の製造方法 |
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DE102008064428B4 (de) * | 2008-12-22 | 2016-02-25 | Austriamicrosystems Ag | Chipaufbau und Verfahren zur Herstellung eines Chipaufbaus |
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JP2517465B2 (ja) * | 1990-09-28 | 1996-07-24 | 三洋電機株式会社 | リ―ドフレ―ム |
JPH10335366A (ja) * | 1997-05-30 | 1998-12-18 | Sanyo Electric Co Ltd | 半導体装置 |
JPH11135546A (ja) * | 1997-10-31 | 1999-05-21 | Nec Corp | 樹脂封止型半導体装置及びその製造方法 |
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