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JPH10335366A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPH10335366A
JPH10335366A JP9142229A JP14222997A JPH10335366A JP H10335366 A JPH10335366 A JP H10335366A JP 9142229 A JP9142229 A JP 9142229A JP 14222997 A JP14222997 A JP 14222997A JP H10335366 A JPH10335366 A JP H10335366A
Authority
JP
Japan
Prior art keywords
semiconductor chip
pad
bonding
wire
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9142229A
Other languages
English (en)
Inventor
Makoto Tsubonoya
誠 坪野谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP9142229A priority Critical patent/JPH10335366A/ja
Publication of JPH10335366A publication Critical patent/JPH10335366A/ja
Pending legal-status Critical Current

Links

Classifications

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Abstract

(57)【要約】 【課題】 パッドに金属突起を設けることにより、チッ
プへのダメージを回避しつつパッドとパッドとを直接ワ
イヤボンドすることを可能にする。 【解決手段】 アイランド１３上に第１の半導体チップ
１０と第２の半導体チップ１１を固着する。パッド１２
と外部接続リード１５とをボンディングワイヤ１６で接
続する。両半導体チップ１０、１１間で電気接続を行う
べきパッド１２ａのうち一方のパッド１２ａには、バン
プ１７等の金属導体片を形成する。金属導体片の上面は
パッシベーション皮膜２２より上に突出させる。そし
て、第１の半導体チップ１のパッド１２ａにボンディン
グワイヤ１６の１ｓｔボンドを打ち、第２の半導体チッ
プ１１のバンプ１７表面に２ｎｄボンドを打つことによ
り必要な電気接続を行う。

Description

【発明の詳細な説明】
【０００１】
【発明の属する技術分野】本発明は、同一パッケージ内
に複数の半導体チップを収納し、半導体チップ間のワイ
ヤ接続を容易ならしめた半導体装置の製造方法に関す
る。
【０００２】
【従来の技術】半導体装置の封止技術として最も普及し
ているのが、半導体チップの周囲を熱硬化性のエポキシ
樹脂で封止するトランスファーモールド技術である。半
導体チップの支持素材としてリードフレームを用い、リ
ードフレームのアイランドに半導体チップをダイボンド
し、半導体チップのボンディングパッドとリードをワイ
ヤでワイヤボンドし、所望の外形形状を具備する金型内
にリードフレームをセットし、金型内にエポキシ樹脂を
注入、これを硬化させることにより製造する。
【０００３】一方、各種電子機器に対する小型、軽量化
の波はとどまるところを知らず、これらに組み込まれる
半導体装置にも、一層の大容量、高機能、高集積化が望
まれることになる。そこで、以前から発想としては存在
していた（例えば、特開平０５ー１２１６４５号）、１
つのパッケージ内に複数の半導体チップを封止する技術
が注目され、実現化する動きが出てきた。つまり図５
（Ａ）（Ｂ）に示すように、アイランド１上に第１と第
２の半導体チップ２ａ、２ｂを固着し、第１と第２の半
導体チップ２ａ、２ｂのボンディングパッド３とリード
４とをボンディングワイヤ５で接続し、樹脂６で封止し
たものである。
【０００４】回路機能の組み合わせによって第１の半導
体チップ１ａと第２の半導体チップ１ｂとを電気的に接
続する場合は、上述した特開平０５ー１２１６４５号の
様にパッドからパッドに直接ボンディングワイヤを打つ
ことが考えられるが、ボールを形成しない２回目のボン
ディングをパッド上に直接打つと、キャピラリツールの
先端が半導体チップの表面に直接接触して半導体チップ
にダメージを与えることになる。そこで、外部接続リー
ド４の一つを中間点とし、第１の半導体チップ１ａと第
２の半導体チップ１ｂの両方から共通の外部接続リード
４にワイヤを打つか（図示しない）、または図５（Ａ）
（Ｂ）に示した様に、アイランド１とは電気的に絶縁し
た接続導体７をアイランド１上に固着し、接続導体７を
介して両半導体チップ１ａ、１ｂを接続していた。
【０００５】
【発明が解決しようとする課題】しかしながら、前者の
外部接続リードを介して接続する手法はボンディングワ
イヤ５が長くなるので他との接触事故等の要因になる
他、リード端子の本数増大になるという欠点があり、後
者の接続導体７を用いる手法は部品代と工数的に大幅な
コスト高になり、接続導体７を配置することによりパッ
ケージが大型化するという欠点があった。
【０００６】
【課題を解決するための手段】本発明は上述した従来の
課題に鑑み成されたもので、半導体チップのパッド上に
導体片を固着し、該導体片にワイヤの２ｎｄボンドを打
つことにより、キャピラリツールが半導体チップに接触
することなく、第１の半導体チップ１ａと第２の半導体
チップ１ｂとをボンディングワイヤで直接接続すること
を可能ならしめたものである。
【０００７】
【発明の実施の形態】以下に本発明の一実施の形態を図
面を参照しながら詳細に説明する。図１は本発明の半導
体装置を示す（Ａ）平面図、（Ｂ）断面図である。図
中、１０、１１は各々第１と第２の半導体チップ、１２
は第１と第２の半導体チップ１０、１１の表面に形成し
たボンディングパッド、１３は半導体チップ１０、１１
を搭載するためのアイランド、１４は半導体チップ１
０、１１を固着するための接着剤、１５は外部接続リー
ド、１６はパッド１２と外部接続リード１５とを接続す
るボンディングワイヤ、１７は主要部を封止する樹脂を
示している。
【０００８】第１と第２の半導体チップ１０、１１のシ
リコン表面には、前工程において各種の能動、受動回路
素子を形成し、各素子を電極配線で接続することにより
所望の回路機能を達成している。ボンディングパッド１
２は前記電極材料からなり、各チップの周辺部分に複数
個配置されている。各半導体チップ１０、１１の表面に
はボンディングパッド１２を被覆するようにシリコン窒
化膜、シリコン酸化膜、ポリイミド系絶縁膜などのパッ
シベーション皮膜が形成され、ボンディングパッド１２
の上部だけが電気接続のために開口されている。
【０００９】各半導体チップ１０、１１は、リードフレ
ームのアイランド１３上に並べて接着剤１４によりダイ
ボンドされている。基板の導電型が同じ組み合わせであ
る場合は両者共にＡｇペーストなどのエポキシ系導電接
着剤を使用するが、導電型が異なる場合及び基板電位が
異なる場合は、どちらか一方または両方を絶縁性の接着
剤によってダイボンドしている。
【００１０】ボンディングワイヤ１６は直径３０ミクロ
ン程度の金線からなり、ボールボンディング方式により
パッド１２と外部接続リード１５とを電気的に接続す
る。すなわち、先端に金ボールを形成したボンディング
ワイヤ１６を各半導体チップ１０、１１のパッド１２上
に押しつけて１ｓｔボンドとし、キャビラリツールを移
動し、外部接続リード１５の先端部表面に押圧接着する
と共に切断して２ｎｄボンドとする方式である。各半導
体チップ１０、１１の、外部接続リード１５に近接する
３辺に位置するパッド１２は、ボールボンドにより外部
接続リード１５に接続する。残りの各１辺、すなわち、
第１と第２の半導体チップ１０、１１が相対向する辺に
位置するパッド１２ａは、第１の半導体チップ１０から
第２の半導体チップ１１にワイヤボンドして、両者を直
接電気的に接続する。２ｎｄボンド側となる第２の半導
体チップ１１のパッド１２ａ上には、ワイヤとの接続を
介するバンプ１７等の金属導体辺が固着されており、ボ
ンディングワイヤ１６の端部は前記金属導体辺にボンデ
ィングされている。詳細は後述する。
【００１１】第１と第２の半導体チップ１０、１１、外
部接続リード１５の先端部、およびボンディングワイヤ
１６を含む主要部は、周囲をエポキシ系の熱硬化樹脂１
８でモールドし、パッケージ化する。リード端子１５は
パッケージの側壁の、樹脂１８の厚みの約半分の位置か
ら外部に導出される。そして、樹脂１８の外部に導出さ
れたリード端子１５は一端下方に曲げられ、再度曲げら
れてＺ字型にフォーミングされている。このフォーミン
グ形状は、リード端子１５の裏面側固着部分をプリント
基板に形成した導電パターンに対向接着する、表面実装
用途の為の形状である。
【００１２】図２に、相対向する辺に形成したパッド１
２ａ付近の拡大図を示す。パッド１２ａは半導体基板上
の絶縁膜２０の上にアルミなどの電極配線材料で１３０
×１３０μ程度の矩形の大きさで形成され、絶縁膜２０
上を引き回した電極配線２１にて内部回路と接続してい
る。パッド１２ａの上部をパッシベーション皮膜２２が
被覆し、上部に開口部２３を形成してパッド１２ａ表面
を露出している。第２の半導体チップ１１のパッド１２
ａは、２ｎｄボンド用に長方形に拡大しており、その表
面に金又は半田等のバンプ１７が形成されている。バン
プ１７は第２の半導体チップ１１のウェハ工程の最終段
階で、無電界または電解メッキ法によりパッド１２ａ表
面にだけ選択的に形成したもので、パッシベーション皮
膜２２より上に突出するように、例えば高さ１００μ程
度に形成したものである。外部接続リード１５との接続
を行うパッド１２には、バンプ１７を形成してもしなく
ても良い。そして、第１の半導体チップ１０のパッド１
２ａ表面にボンディングワイヤ１６の１ｓｔボンドが打
たれ、２ｎｄボンドがバンプ１７の表面に打たれる。
【００１３】図３、図４にワイヤボンド工程の概略図を
工程順に示した。先ず図３（Ａ）に示すように、キャピ
ラリ２５の貫通孔２６に挿通されたワイヤ１６の先端に
金ボール２７を形成し、該金ボール２７を第１の半導体
チップ１０のパッド１２ａ表面に押圧・加熱超音波振動
により固着して１ｓｔボンドとし、図３（Ｂ）に示すよ
うにキャピラリ２５を上方向、続いて横方向に移動し
て、図３（Ｃ）に示すようにバンプ１７上部にワイヤ１
６を再度押圧・加熱超音波振動により固着して２ｎｄボ
ンドとする。前記２ｎｄボンドの時は、図４に示すよう
に、キャピラリ２５の先端部２８でワイヤ１６を押潰す
ことによりワイヤ１６を切断するので、先端部２８が被
固着面２９に機械的に直接接触することになる。しかし
本発明では、パッド１２ａ上に形成したバンプ１７の上
に２ｎｄボンドを打ち、バンプ１７の被固着面２９がパ
ッシベーション皮膜２２より上方に位置するので、キャ
ピラリの先端部２８が第２の半導体チップ１１表面にダ
メージを与えることがない。
【００１４】そして図４（Ｂ）に示すように、キャピラ
リ２５上方に位置する図示せぬクランパがワイヤ１６を
挟み固定し、その状態でキャピラリ２５を上方に移動す
ることにより、２ｎｄボンドされたワイヤ１６と貫通孔
２６内部のワイヤとを分離する。以上に説明したよう
に、本発明では第２の半導体チップ１０上のボンディン
グパッド１２ａ上にバンプ１７を形成し、チップ表面よ
り突出した該バンプ１７上にワイヤ１６の２ｎｄボンド
を打つので、キャピラリ２５によって半導体チップ表面
にダメージを与えることなく、第１の半導体チップ１０
と第２の半導体チップ１１とを直接ボンディングワイヤ
１６で接続できるものである。
【００１５】尚、バンプ１７の他にも、例えば金、アル
ミ等の金属片をパッド１２ａ上に接着剤で固着しても良
く、要はボンディングワイヤ１６が接続可能な材料で、
その固着表面２９がパッシベーション皮膜２２より高い
位置に存在し、その大きさがキャピラリ２５先端部分２
８の大きさより大であればよい。
【００１６】
【発明の効果】以上に説明した通り、本発明によれば、
チップにダメージを与えることなく第１の半導体チップ
１０と第２の半導体チップ１１とを直接ボンディングワ
イヤ１６で接続できる利点を有する。その為、複数の半
導体チップを収納した半導体装置を安価に製造すること
ができる利点を有する。更に、従来例のように接続を仲
介する部分がないので、半導体装置の横方向の寸法を縮
小できる利点を有する他、部品代等のコストを大幅に減
じることができる。
【図面の簡単な説明】
【図１】本発明を説明するための（Ａ）平面図、（Ｂ）
断面図である。
【図２】本発明のパッド１２ａ付近を示す（Ａ）断面
図、（Ｂ）平面図である。
【図３】ワイヤボンド工程を説明するための断面図であ
る。
【図４】ワイヤボンド工程を説明するための断面図であ
る。
【図５】従来例を説明するための（Ａ）平面図、（Ｂ）
断面図である。

Claims (3)

    【特許請求の範囲】
  1. 【請求項１】 アイランドの上に少なくとも２個の半導
    体チップを並べて設置し、前記半導体チップ上のボンデ
    ィングパッドと外部接続リードとをボンディングワイヤ
    で各々接続し、更に前記半導体チップのボンディングパ
    ッドと他の半導体チップのボンディングパッドとをボン
    ディングワイヤで接続し、主要部を封止した半導体装置
    であって、 前記半導体チップのボンディングパッド上に１ｓｔボン
    ドを打つと共に、前記他の半導体チップのボンディング
    パッドに導体片が固着され、前記導体片に前記ボンディ
    ングワイヤの２ｎｄボンドが打たれていることを特徴と
    する半導体装置。
  2. 【請求項２】 前記ワイヤボンディングがボールボンド
    であることを特徴とする請求項１記載の半導体装置。
  3. 【請求項３】 前記導体片が金バンプ又は半田バンプで
    あることを特徴とする請求項１記載の半導体装置。
JP9142229A 1997-05-30 1997-05-30 半導体装置 Pending JPH10335366A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9142229A JPH10335366A (ja) 1997-05-30 1997-05-30 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9142229A JPH10335366A (ja) 1997-05-30 1997-05-30 半導体装置

Publications (1)

Publication Number Publication Date
JPH10335366A true JPH10335366A (ja) 1998-12-18

Family

ID=15310432

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9142229A Pending JPH10335366A (ja) 1997-05-30 1997-05-30 半導体装置

Country Status (1)

Country Link
JP (1) JPH10335366A (ja)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100491234B1 (ko) * 2001-12-03 2005-05-25 미쓰비시덴키 가부시키가이샤 반도체 집적 회로 장치
JP2006261542A (ja) * 2005-03-18 2006-09-28 Nec Electronics Corp 半導体装置及びその製造方法
JP2007220790A (ja) * 2006-02-15 2007-08-30 Renesas Technology Corp 半導体装置およびその製造方法
JP2008028414A (ja) * 2007-09-14 2008-02-07 Renesas Technology Corp 半導体装置
JP2009295988A (ja) * 2008-06-09 2009-12-17 Micronas Gmbh 特別に形作られたボンドワイヤを有する半導体装置およびそのような装置を製造するための方法
JP2014220439A (ja) * 2013-05-10 2014-11-20 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置
CN107785347A (zh) * 2016-08-24 2018-03-09 三星显示有限公司 半导体芯片和电子装置

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100491234B1 (ko) * 2001-12-03 2005-05-25 미쓰비시덴키 가부시키가이샤 반도체 집적 회로 장치
US7148567B2 (en) 2001-12-03 2006-12-12 Renesas Technology Corp. Semiconductor integrated circuit device
JP2006261542A (ja) * 2005-03-18 2006-09-28 Nec Electronics Corp 半導体装置及びその製造方法
JP4666592B2 (ja) * 2005-03-18 2011-04-06 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP2007220790A (ja) * 2006-02-15 2007-08-30 Renesas Technology Corp 半導体装置およびその製造方法
JP2008028414A (ja) * 2007-09-14 2008-02-07 Renesas Technology Corp 半導体装置
JP2009295988A (ja) * 2008-06-09 2009-12-17 Micronas Gmbh 特別に形作られたボンドワイヤを有する半導体装置およびそのような装置を製造するための方法
JP2014220439A (ja) * 2013-05-10 2014-11-20 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置
CN107785347A (zh) * 2016-08-24 2018-03-09 三星显示有限公司 半导体芯片和电子装置
CN107785347B (zh) * 2016-08-24 2023-08-15 三星显示有限公司 半导体芯片和电子装置

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