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JP3378809B2 - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JP3378809B2
JP3378809B2 JP27800798A JP27800798A JP3378809B2 JP 3378809 B2 JP3378809 B2 JP 3378809B2 JP 27800798 A JP27800798 A JP 27800798A JP 27800798 A JP27800798 A JP 27800798A JP 3378809 B2 JP3378809 B2 JP 3378809B2
Authority
JP
Japan
Prior art keywords
bonding
bonding pad
ball
semiconductor chip
wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP27800798A
Other languages
English (en)
Other versions
JP2000114452A (ja
Inventor
誠 坪野谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP27800798A priority Critical patent/JP3378809B2/ja
Publication of JP2000114452A publication Critical patent/JP2000114452A/ja
Application granted granted Critical
Publication of JP3378809B2 publication Critical patent/JP3378809B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
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    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0657—Stacked arrangements of devices
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    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06506—Wire or wire-like electrical connections between devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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Description

【発明の詳細な説明】
【０００１】
【発明の属する技術分野】本発明は、複数の半導体チッ
プを重ね合わせてモールドしつつ、パッケージ外形の薄
型化が可能な、半導体装置に関する。
【０００２】
【従来の技術】半導体装置の封止技術として最も普及し
ているのが、図３（Ａ）に示したような、半導体チップ
１の周囲を熱硬化性のエポキシ樹脂２で封止するトラン
スファーモールド技術である。半導体チップ１の支持素
材としてリードフレームを用いており、リードフレーム
のアイランド３に半導体チップ１をダイボンドし、半導
体チップ１のボンディングパッドとリード４をワイヤ５
でワイヤボンドし、所望の外形形状を具備する金型内に
リードフレームをセットし、金型内にエポキシ樹脂を注
入、これを硬化させることにより製造される。
【０００３】一方、各種電子機器に対する小型、軽量化
の波はとどまるところを知らず、これらに組み込まれる
半導体装置にも、一層の大容量、高機能、高集積化が望
まれることになる。
【０００４】そこで、以前から発想としては存在してい
た（例えば、特開昭５５ー１１１１５１７号）、１つの
パッケージ内に複数の半導体チップを封止する技術が注
目され、実現化する動きが出てきた。つまり図３（Ｂ）
に示すように、アイランド３上に第１の半導体チップ１
ａを固着し、第１の半導体チップ１ａの上に第２の半導
体チップ１ｂを固着し、対応するボンディングパッドと
リード４とを第１と第２のボンディングワイヤ５ａ、５
ｂで接続し、樹脂２で封止したものである。
【０００５】
【発明が解決しようとする課題】コストアップになるに
も関わらず複数のチップを一体化させることは、即ち軽
薄短小化の要求が極めて強いからに他ならない。故に外
形寸法に余裕のあるＤＩＰ型パッケージよりは、表面実
装型の、しかも薄型のパッケージに収納したい意向が強
く、その方が全体としてのメリットが大きい。
【０００６】しかしながら、半導体チップ１には、機械
的強度を持たせる必要性から、ある程度の厚み以上には
薄くすることができないので、チップを積層した分だけ
パッケージ外形を大型化する欠点がある。
【０００７】また、第２のボンディングワイヤ５ｂは、
第１の半導体チップ１ａとの接触を避けることと、第１
のボンディングワイヤ５ａと交差したときの接触を避け
るという意味で、ワイヤループを相当大きく取る必要性
が生じる。そのため、ワイヤループの高さ６が大きくな
りがちであり、これがパッケージ全体の厚みを厚くし
て、薄形化を阻害するという欠点があった。
【０００８】
【課題を解決するための手段】本発明は上述した従来の
課題に鑑み成されたもので、第１のボンディングパッド
を有する第１の半導体チップと、第２のボンディングパ
ッドを有し前記第１の半導体チップの上に固着された第
２の半導体チップと、前記第１と第２のボンディングパ
ッドに電気的に接続すべき内部電極と、前記第１のボン
ディングパッドの表面に形成したボールバンプと、前記
第２のボンディングパッドと前記ボールバンプとを接続
する第１のワイヤと、前記ボールバンプと前記内部電極
とを接続する第２のワイヤと、前記第１と第２の半導体
チップの周囲を被覆する絶縁樹脂と、を具備することを
特徴とするものである。
【０００９】
【発明の実施の形態】以下に本発明の一実施の形態を図
面を参照しながら詳細に説明する。
【００１０】先ず、図１（Ａ）は本発明の半導体装置を
示す断面図、図１（Ｂ）は要部拡大断面図である。
【００１１】図中、１０、１１は各々第１と第２の半導
体チップを示している。第１と第２の半導体チップ１
０、１１のシリコン表面には、前工程において各種の能
動、受動回路素子が形成されている。第１の半導体チッ
プ１０の表面には外部接続用の第１のボンディングパッ
ド１２ａが形成されている。同様に第２の半導体チップ
１１の表面には第２のボンディングパッド１２ｂが形成
されている。各チップ表面には各ボンディングパッド１
２ａ、１２ｂを被覆するようにシリコン窒化膜、シリコ
ン酸化膜、ポリイミド系絶縁膜などのパッシベーション
皮膜が形成され、ボンディングパッド１２ａ、１２ｂの
上部は電気接続のために開口されている。
【００１２】絶縁性のフィルム基板１３は、これら第１
と第２の半導体チップ１０、１１を支持する基板とな
る。フィルム基板１３の表面には金メッキ層によって導
電パターンが描画されている。導電パターンは、各ボン
ディングパッド１２ａ、１２ｂとバンプ電極２０とを各
々接続するための内部電極１４とを形成する。
【００１３】第１の半導体チップ１０は、前記アイラン
ド部の上に導電性又は絶縁性の接着剤１５により固着さ
れている。第２の半導体チップ１１は第１の半導体チッ
プ１０の前記パッシベーション皮膜上に絶縁性のエポキ
シ系接着剤１５により固着されている。但し第２の半導
体チップ１１は第１のボンディングパッド１２ａを被覆
しないチップサイズである。
【００１４】第１のボンディングパッド１２ａの上部に
は、ボールバンプ１７が形成されている。ボールバンプ
１７は、金ワイヤのボールボンディング手法を利用し
て、金ボール部分だけを残す形で形成したバンプ電極で
ある。そして、第２のボンディングパッド１２ｂとボー
ルバンプ１７とが第２のボンディングワイヤ１８によっ
て接続され、ボールバンプ１７と内部電極１４とが第２
のボンディングワイヤ１９によって接続されている。
【００１５】第２のボンディングワイヤ１８は第２の電
極パッド１２ｂ側をファーストボンドとするボールボン
ディングにより、第２のボンディングワイヤ１９はボー
ルバンプ１７側をファーストボンドとするボールボンデ
ィングにより、各々形成されている。順番としては、先
にボールバンプ１７を形成し、次いで第２のボンディン
グワイヤ１８を第２のボンディングパッド１２ｂからボ
ールバンプ１７に向けてボンディングし、そして第１の
ボンディングワイヤ１９をボールバンプ１７から内部電
極１４に向けてボンディングする。このボールバンプ１
７は、第２のボンディングワイヤ１８をセカンドボンド
（ステッチボンド）する際に、ボンディングツールの先
端が第１の半導体チップ１０の表面に直接当接する事を
防止する緩衝剤となる。
【００１６】複数のバンプ電極２０が、フィルム基板１
３の裏面側に形成されている。フィルム基板１３には図
示せぬ貫通孔が設けられており、この貫通孔を介して内
部電極１４とバンプ電極２０とが接続している。
【００１７】エポキシ系の熱硬化樹脂２１が、第１と第
２の半導体チップ１０、１１の周囲を被覆する。熱硬化
性樹脂２１はフィルム基板１３の上側を被覆して、パッ
ケージ外形を形成する。
【００１８】第１と第２の半導体チップ１０、１１は、
メモリ装置で組み合わせることが簡便である。例えば、
第１と第２の半導体チップ１０、１１としてＥＥＰＲＯ
Ｍ（フラッシュメモリ）等の半導体記憶装置を用いた場
合（第１の組み合わせ例）は、１つのパッケージで記憶
容量を２倍、３倍・・・にすることができる。また、第
１の半導体チップ１０にＥＥＰＲＯＭ（フラッシュメモ
リ）等の半導体記憶装置を、第２の半導体チップ１１に
はＳＲＡＭ等の半導体記憶装置を形成するような場合
（第２の組み合わせ例）も考えられる。
【００１９】どちらの組み合わせの場合でも、各チップ
にはデータの入出力を行うＩ／Ｏ端子と、データのアド
レスを指定するアドレス端子、及びデータの入出力を許
可するチップイネーブル端子とを具備しており、両チッ
プのピン配列が酷似している。そのため、第１と第２の
半導体チップ１０、１１のＩ／Ｏ端子やアドレス端子用
の内部電極１４を共用することが可能であり、各チップ
に排他的なチップイネーブル信号を印加することによ
り、どちらか一方の半導体チップのメモリセルを排他的
に選択することが可能である。また、斯かる構成によっ
て、第１と第２のボンディングパッド１２ａ、１２ｂを
電気的に接続することが可能となる。
【００２０】尚、第１と第２のボンディングパッド１２
ａ、１２ｂを電気的に接続できない回路構成である場合
は、第１のボンディングパッド１２ａを電気的に独立さ
せて回路的な機能を持たないダミーのパッドとし、該ダ
ミーパッド上にボールバンプ１７を形成して、図１のよ
うに２本のワイヤで接続する。
【００２１】図２は、ボールバンプ１７の製造方法を簡
単に説明するための断面図である。
【００２２】図２（Ａ）参照：キャピラリ３０の中心孔
３１に直径が２０〜３０μ程度の金ワイヤ３２を挿通
し、そのワイヤ３２の先端にあらかじめスパークなどの
手段によって直径が６０〜８０μの金ボール３３を形成
しておく。これを第１のボンディングパッド１２ａ上方
に移動し、キャピラリ３０を下降させることにより、金
ボール３３を電極パッド１２ａ表面に当接し、一定の圧
力を加える。同時にキャピラリ１２を通して超音波振動
を与え且つ加熱して、金ボール３３と第１のボンディン
グパッド１２ａとを固着する。
【００２３】図２（Ｂ）参照：キャピラリ３０を垂直に
上昇させ、再度垂直に下降させる。キャピラリ３０の先
端と金ボール３３の上端（平坦部）との距離３４が１０
〜３０μｍとなるような位置でキャピラリ３０を停止す
る。金ボール３３の付け根付近はキャピラリ３０内部に
収納されず、露出した状態となる。
【００２４】図２（Ｃ）参照：上記の距離３４を維持し
た上で、金ワイヤ３２の直径の３分の２を超える距離だ
けキャピラリ３０を水平移動する。例えば、キャピラリ
１２先端部の穴の直径が４０μであるときは２５μ〜３
５μだけ移動する。金ワイヤ３２はキャピラリ３０の先
端部で途中まで剪断され、糸を引くように細い部分３５
でかろうじて連続している状態となる。
【００２５】本工程で剪断を与えるために、距離３４は
重要な意味を持つ。この距離３４が大きすぎると金ワイ
ヤ３２が塑性変形するだけで細い部分３５を作れなくな
るし、距離３４が小さすぎると、接合した金ボール１７
を剥がすことになる。キャピラリ３０の先端が、図２
（Ｄ）に示したように、金ボール３３の付け根近傍で、
塑性変形の影響を受けずに金ワイヤ３２が本来の直径Φ
１を維持した部分の直ぐ上部に位置するようにコントロ
ールする。
【００２６】図２（Ｅ）参照：再びキャピラリ３０を垂
直上昇させた状態を示している。金ワイヤ３２と金ボー
ル３３とが細い部分３５だけで連続している状態を示し
た。
【００２７】図２（Ｆ）参照：今まで解放していた図示
せぬクランパを閉じて金ワイヤ３２を挟持し、上方に引
き上げることで細い部分３５を完全に切断する。この様
な工程により第１のボンディングパッド１２ａ上部にボ
ールバンプ１７が形成される。
【００２８】以上に説明した本発明の半導体装置は、第
２のボンディングパッド１２ｂを第１のボンディングパ
ッド１２ａに接続することによって、両者の距離が近い
ので、第２のボンディングワイヤ１８のループ長さを短
くすることが可能である。従って、ループ高さ２２（図
１）を低く押さえることができる。これは、第１の半導
体チップ１０と第２の半導体チップ１１とのチップサイ
ズの差が大きい場合に特に有効になる。そして、第２の
ボンディングワイヤ１８と第１の半導体チップ１０との
接触事故を回避することができ、更には、第１と第２の
ボンディングワイヤ１８、１９が交差しないので、電気
的短絡をも回避することができる。
【００２９】
【発明の効果】以上に説明した通り、本発明によれば、
１つのパッケージ内に複数の半導体チップ１０、１１を
積層する事により、電子機器の軽薄短小化の要求に沿っ
た高密度実装の製品を提供できる利点を有する。
【００３０】また、第１のボンディングワイヤ１８と内
部電極１４とを、第１のボンディングパッド１２ａを介
して接続するので、第２のボンディングワイヤ１８の長
さを短くできる利点を有する。これにより、ループ高さ
２２を低く抑えることができるので、パッケージの厚み
を薄形化できる利点を有する。
【００３１】そして、第２のボンディングパッド１２ｂ
から内部電極１４に直接ワイヤボンドしないので、第１
と第２のボンディングワイヤ１８、１９の交差が無くな
り、電気的短絡という事故を防ぐ他、第２のボンディン
グワイヤ１８と第１の半導体チップ１０との接触をも防
止することができる。
【００３２】更に内部電極１４へのステッチボンドが１
本で済むので、ボンディングエリアを小さくすることが
でき、半導体装置の小型化を図ることができる。
【図面の簡単な説明】
【図１】本発明を説明するための断面図である。
【図２】本発明を説明するための断面図である。
【図３】従来例を説明するための断面図である。

Claims (3)

    (57)【特許請求の範囲】
  1. 【請求項１】 第１のボンディングパッドを有する第１
    の半導体チップと、 第２のボンディングパッドを有し前記第１の半導体チッ
    プの上に固着された第２の半導体チップと、 前記第１と第２のボンディングパッドに電気的に接続す
    べき内部電極と、 前記第１のボンディングパッドの表面に形成したボール
    バンプと、前記第２のボンディングパッドにファーストボンドされ
    前記ボールバンプ上にセカンドボンドされたボールボン
    ディングにより接続する 第１のワイヤと、前記ボールバンプ上にファーストボンドされ前記内部電
    極にセカンドボンドされたボールボンディングにより接
    続する 第２のワイヤと、 前記第１と第２の半導体チップの周囲を被覆する絶縁樹
    脂と、を具備することを特徴とする半導体装置。
  2. 【請求項２】 前記第１のボンディングパッドが電気的
    にダミーであり、前記第２のボンディングパッドが前記
    第１のボンディングパッドを介して前記内部電極に接続
    されていることを特徴とする請求項１記載の半導体装
    置。
  3. 【請求項３】 前記第１のボンディングパッドと前記第
    ２のボンディングパッドとが共通の機能を有する事を特
    徴とする請求項１記載の半導体装置。
JP27800798A 1998-09-30 1998-09-30 半導体装置 Expired - Lifetime JP3378809B2 (ja)

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Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3765952B2 (ja) * 1999-10-19 2006-04-12 富士通株式会社 半導体装置
JP2002217367A (ja) 2001-01-15 2002-08-02 Mitsubishi Electric Corp 半導体チップ、半導体装置および半導体装置の製造方法
US20020145190A1 (en) * 2001-04-10 2002-10-10 Fernandez Joseph D. Arrangement and method of arrangement of stacked dice in an integrated electronic device
JP3865055B2 (ja) 2001-12-28 2007-01-10 セイコーエプソン株式会社 半導体装置の製造方法
JP3727272B2 (ja) 2002-01-15 2005-12-14 沖電気工業株式会社 半導体装置及び半導体装置の製造方法
JP2005268497A (ja) 2004-03-18 2005-09-29 Denso Corp 半導体装置及び半導体装置の製造方法
JP4666592B2 (ja) 2005-03-18 2011-04-06 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US20060289981A1 (en) * 2005-06-28 2006-12-28 Nickerson Robert M Packaging logic and memory integrated circuits
JP2008034567A (ja) 2006-07-27 2008-02-14 Fujitsu Ltd 半導体装置及びその製造方法
US8008785B2 (en) 2009-12-22 2011-08-30 Tessera Research Llc Microelectronic assembly with joined bond elements having lowered inductance

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