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JP2821408B2 - Semiconductor wafer - Google Patents

Semiconductor wafer

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Publication number
JP2821408B2
JP2821408B2 JP8005892A JP589296A JP2821408B2 JP 2821408 B2 JP2821408 B2 JP 2821408B2 JP 8005892 A JP8005892 A JP 8005892A JP 589296 A JP589296 A JP 589296A JP 2821408 B2 JP2821408 B2 JP 2821408B2
Authority
JP
Japan
Prior art keywords
wafer
thickness
grinding
edge
tip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP8005892A
Other languages
Japanese (ja)
Other versions
JPH09199378A (en
Inventor
泰信 斎藤
Original Assignee
山形日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 山形日本電気株式会社 filed Critical 山形日本電気株式会社
Priority to JP8005892A priority Critical patent/JP2821408B2/en
Publication of JPH09199378A publication Critical patent/JPH09199378A/en
Application granted granted Critical
Publication of JP2821408B2 publication Critical patent/JP2821408B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Mechanical Treatment Of Semiconductor (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は半導体ウェーハに関
し、特にデバイス素子が形成され裏面が研削された大口
径の半導体ウェーハの形状に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor wafer, and more particularly, to a large-diameter semiconductor wafer having device elements formed and a back surface ground.

【0002】[0002]

【従来の技術】半導体装置の製造工程においては、半導
体ウェーハ(以下単にウェーハという)の平坦な表面に
デバイス素子が形成されるが、ウェーハの端面はフォト
リソグラフィ工程でのレジスト膜の厚さを制限したり端
面の欠けを少くする為に丸みを有する形状となってい
る。
2. Description of the Related Art In the process of manufacturing a semiconductor device, device elements are formed on a flat surface of a semiconductor wafer (hereinafter simply referred to as a wafer), but the end face of the wafer limits the thickness of a resist film in a photolithography process. It has a rounded shape to reduce chipping and chipping of the end face.

【0003】近年、ウェーハの大口径化が進められてい
るが、それに伴ってウェーハの厚さも8インチのもので
725μm,12インチのもので775μmと厚くなっ
てきている。ウェーハの大口径化は必然的に半導体チッ
プの体積を増加させることになる為、図2に示すよう
に、表面1Aにデバイス素子が形成された厚さTのウェ
ーハ1の裏面1Bは研削されて250〜300μmの厚
さtとされ、次の工程に送られている。
In recent years, the diameter of wafers has been increased, and accordingly, the thickness of wafers has been increased to 725 μm for 8-inch wafers and 775 μm for 12-inch wafers. Since the increase in the diameter of the wafer inevitably increases the volume of the semiconductor chip, as shown in FIG. 2, the back surface 1B of the wafer 1 having a thickness T in which device elements are formed on the front surface 1A is ground. It has a thickness t of 250 to 300 μm and is sent to the next step.

【0004】しかしながら、このように研削されたウェ
ーハ2のエッジ部4の水平距離lは研削後のウェーハ2
の厚さtに比べて長く、その先端5は薄くて尖っている
為、その後の半導体装置の製造工程で製造装置と機械的
に接触し、エッジ部4が欠け、半導体チップに付着して
パターンをショートさせたり、研削後のウェーハ2に割
れを発生させたりして、半導体装置の製造歩留りを低下
させるという欠点があった。
[0004] However, the horizontal distance l of the edge portion 4 of the wafer 2 thus ground is equal to the wafer 2 after the grinding.
Is longer than the thickness t of the semiconductor device, and its tip 5 is thin and sharp, so that it comes into mechanical contact with the manufacturing equipment in the subsequent manufacturing process of the semiconductor device, and the edge portion 4 is chipped and adheres to the semiconductor chip. There is a drawback that the semiconductor device manufacturing yield is reduced by short-circuiting the wafer or causing cracks in the wafer 2 after grinding.

【0005】この対策として図3に示すように、裏面の
研削後もウェーハ2の最端面3Aに丸味とテーパ形状が
残る位置に、ラウンドエッジを設定する方法が、例えば
特開平4−34931号公報に提案されている。図3に
おいてtは研削後のウェーハ2の厚さ、t1 はエッジ部
最端面の厚さである。
As a countermeasure for this, as shown in FIG. 3, a method of setting a round edge at a position where a roundness and a tapered shape remain on the outermost end surface 3A of the wafer 2 even after grinding the back surface is disclosed in, for example, JP-A-4-34931. Has been proposed. In FIG. 3, t is the thickness of the wafer 2 after grinding, and t 1 is the thickness of the edge end surface.

【0006】[0006]

【発明が解決しようとする課題】しかしながら、図3で
説明した従来の半導体ウェーハにおいては、研削前に最
端面を細く尖った形状にしておく為、研削前の半導体素
子形成工程等においてウェーハのエッジ部が欠けたり、
ウェーハ自体が割れたりするという新たな問題点がある
ことが分った。
However, in the conventional semiconductor wafer described with reference to FIG. 3, since the outermost end face is made thin and sharp before grinding, the edge of the wafer is formed in a semiconductor element forming step before grinding. Part is missing,
It has been found that there is a new problem that the wafer itself is cracked.

【0007】本発明の目的は、上記問題点を解決し、研
削前後の工程においてもウェーハエッジ部の欠けやウェ
ーハの割れの発生を抑制できる半導体ウェーハを提供す
ることにある。
An object of the present invention is to solve the above problems and to provide a semiconductor wafer capable of suppressing occurrence of chipping of a wafer edge portion and cracking of a wafer in processes before and after grinding.

【0008】[0008]

【課題を解決するための手段】本発明の半導体ウェーハ
は、端面の形状が丸みを有するウェーハの平坦な表面に
デバイス素子を形成し、このウェーハの裏面を研削して
規定の厚さに形成した半導体ウェーハにおいて、平坦な
前記ウェーハの表面の端から研削後の前記ウェーハのエ
ッジ部先端迄の水平距離を前記規定の厚さより小さくし
たことを特徴とするものである。
In the semiconductor wafer of the present invention, device elements are formed on a flat surface of a wafer having a rounded end surface, and the back surface of the wafer is ground to a specified thickness. In a semiconductor wafer, a horizontal distance from an edge of a flat surface of the wafer to a tip of an edge portion of the wafer after grinding is smaller than the specified thickness.

【0009】[0009]

【発明の実施の形態】次に本発明について図面を参照し
て説明する。図1は本発明の一実施の形態を説明する為
のウェーハの断面図である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of a wafer for explaining an embodiment of the present invention.

【0010】図1において厚さTのウェーハ1は、その
端面3の形状が丸みを有しており、平坦な表面1Aにデ
バイス素子を形成したのち、平坦な裏面1Bを研削し規
定の厚さtにした場合、平坦なウェーハの表面1A,1
Bの端部(点P,Q)から研削後のウェーハ2のエッジ
部先端5までの水平距離Lをtより小さくしている。以
下端面3の円弧を楕円とした場合について具体的に説明
する。
In FIG. 1, a wafer 1 having a thickness T has a rounded end face 3, and after a device element is formed on a flat surface 1A, the flat back surface 1B is ground to form a specified thickness. t, the flat wafer surfaces 1A, 1
The horizontal distance L from the end of B (points P and Q) to the tip 5 of the edge of the wafer 2 after grinding is set smaller than t. Hereinafter, a case where the arc of the end face 3 is an ellipse will be specifically described.

【0011】ウェーハ1の厚さTを775μm、研削後
のウェーハ2の厚さtを250μm、平坦なウェーハ表
面の端部P,Qを結ぶu軸とウェーハ1の厚さの中心を
通るv軸との交点を0とし、v軸と端面3の円弧との交
点をAとすると、端面3の円弧が含まれ楕円は次の
(1)式で表わされる。
The thickness T of the wafer 1 is 775 μm, the thickness t of the wafer 2 after grinding is 250 μm, the u-axis connecting the ends P and Q of the flat wafer surface and the v-axis passing through the center of the thickness of the wafer 1. Is 0, and the intersection of the v-axis and the arc of the end face 3 is A. The ellipse including the arc of the end face 3 is expressed by the following equation (1).

【0012】 u2 /(T/2)2 +v2 /A2 =1 ・・・(1) 次にこの時のエッジ部先端5の座標(v,u)を求め
る。(1)式にT=775μm、u=387.5μm−
250μm=137.5μmを代入すると、v=0.9
35Aとなる。
U 2 / (T / 2) 2 + v 2 / A 2 = 1 (1) Next, the coordinates (v, u) of the edge tip 5 at this time are obtained. In equation (1), T = 775 μm and u = 387.5 μm−
Substituting 250 μm = 137.5 μm, v = 0.9
35A.

【0013】エッジ部先端5迄の水平距離Lと研削後の
ウェーハ2の厚さtが等しい場合は0.935A=25
0μmよりA=267μmとなる。本発明ではtよりL
を小さくする。例えばL=0.9tに設定すればA=2
41μmとなる。すなわち端面3の円弧が含まれる楕円
の式はu2 /(387.5)2 +v2 /(241)2
1と表わされる。
0.935A = 25 when the horizontal distance L to the edge tip 5 is equal to the thickness t of the wafer 2 after grinding.
A becomes 267 μm from 0 μm. In the present invention, from t, L
Smaller. For example, if L = 0.9t, A = 2
It becomes 41 μm. That is, the formula of the ellipse including the arc of the end face 3 is u 2 /(387.5) 2 + v 2 / (241) 2 =
Expressed as 1.

【0014】このような楕円の軌跡からなる円弧を持つ
端面のウェーハ1を形成するには、このウェーハ端面の
プロファイルでウェーハ加工用の刃物を作成し、ウェー
ハを回転させながらウェーハの端面を加工すればよい。
この加工によりウェーハ1を研削した場合、研削後のウ
ェーハの厚さtより小さいエッジ部先端までの水平距離
Lを有するウェーハが得られる。
In order to form the wafer 1 having an end surface having an arc formed by such an elliptical trajectory, a blade for processing the wafer is formed with the profile of the end surface of the wafer, and the end surface of the wafer is processed while rotating the wafer. I just need.
When the wafer 1 is ground by this processing, a wafer having a horizontal distance L to the tip of the edge portion smaller than the thickness t of the ground wafer is obtained.

【0015】このように構成されたウェーハ1によれ
ば、研削後のウェーハ2の厚さtより、平坦なウェーハ
表面の端から研削後のウェーハのエッジ部先端迄の水平
距離Lを小さくできる為、従来のウェーハのようにエッ
ジ部は薄くて長くなることはなく、又エッジ部先端の角
度も直角に近づき尖さはなくなる。この為、半導体装置
の全ての製造工程においてウェーハのエッジ部先端の欠
けやウェーハ自体の割れの発生は抑制されたものとなっ
た。ウェーハの研削工程終了時迄に発生した何らかの微
少な欠けは従来約30%のウェーハに発生したが、本実
施の形態によれば10%以下にまで低減させることがで
きた。
According to the wafer 1 configured as described above, the horizontal distance L from the edge of the flat wafer surface to the edge of the edge of the ground wafer can be made smaller than the thickness t of the ground wafer 2. However, unlike the conventional wafer, the edge portion is not thin and long, and the angle of the tip of the edge portion becomes close to a right angle and the sharpness disappears. For this reason, in all the manufacturing steps of the semiconductor device, chipping of the tip of the edge portion of the wafer and generation of cracks in the wafer itself were suppressed. Some small chipping that occurred before the end of the wafer grinding process occurred in about 30% of wafers in the past, but according to the present embodiment, it could be reduced to 10% or less.

【0016】尚、上記実施の形態においてはウェーハ1
の厚さTを775μm,研削後のウェーハの厚さtを2
50μmとした場合について説明したが、これらの厚さ
は適宜変更できることは勿論である。
In the above embodiment, the wafer 1
Is 775 μm, and the thickness t of the wafer after grinding is 2
Although the case where the thickness is set to 50 μm has been described, it is needless to say that these thicknesses can be appropriately changed.

【0017】[0017]

【発明の効果】以上説明したように本発明は、平坦なウ
ェーハの表面の端から研削後のウェーハのエッジ部先端
迄の水平距離を研削後のウェーハの厚さより小さくする
ことにより、半導体装置の製造工程においてウェーハエ
ッジ部の欠けやウェーハの割れの発生を抑制できるとい
う効果がある。
As described above, according to the present invention, the horizontal distance from the edge of the flat wafer surface to the tip of the edge of the wafer after grinding is made smaller than the thickness of the wafer after grinding. In the manufacturing process, there is an effect that occurrence of chipping of the wafer edge portion and cracking of the wafer can be suppressed.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施の形態を説明する為のウェーハの
断面図。
FIG. 1 is a cross-sectional view of a wafer for describing an embodiment of the present invention.

【図2】従来のウェーハの断面図。FIG. 2 is a cross-sectional view of a conventional wafer.

【図3】従来の他のウェーハの断面図。FIG. 3 is a cross-sectional view of another conventional wafer.

【符号の説明】[Explanation of symbols]

1 ウェーハ 1A 表面 1B 裏面 2 研削後のウェーハ 3 端面 3A 最端面 4 エッジ部 5 エッジ部先端 DESCRIPTION OF SYMBOLS 1 Wafer 1A Front surface 1B Back surface 2 Wafer after grinding 3 End face 3A Top end face 4 Edge part 5 Edge part tip

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 端面の形状が丸みを有するウェーハの平
坦な表面にデバイス素子を形成し、このウェーハの裏面
を研削して規定の厚さに形成した半導体ウェーハにおい
て、平坦な前記ウェーハの表面の端から研削後の前記ウ
ェーハのエッジ部先端迄の水平距離を前記規定の厚さよ
り小さくしたことを特徴とする半導体ウェーハ。
1. A semiconductor wafer in which device elements are formed on a flat surface of a wafer having a rounded end surface, and the back surface of the wafer is ground to a specified thickness. A semiconductor wafer wherein a horizontal distance from an edge to a tip of an edge portion of the wafer after grinding is smaller than the specified thickness.
JP8005892A 1996-01-17 1996-01-17 Semiconductor wafer Expired - Fee Related JP2821408B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8005892A JP2821408B2 (en) 1996-01-17 1996-01-17 Semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8005892A JP2821408B2 (en) 1996-01-17 1996-01-17 Semiconductor wafer

Publications (2)

Publication Number Publication Date
JPH09199378A JPH09199378A (en) 1997-07-31
JP2821408B2 true JP2821408B2 (en) 1998-11-05

Family

ID=11623555

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8005892A Expired - Fee Related JP2821408B2 (en) 1996-01-17 1996-01-17 Semiconductor wafer

Country Status (1)

Country Link
JP (1) JP2821408B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7258931B2 (en) * 2002-08-29 2007-08-21 Samsung Electronics Co., Ltd. Semiconductor wafers having asymmetric edge profiles that facilitate high yield processing by inhibiting particulate contamination
JP5934491B2 (en) * 2011-10-25 2016-06-15 株式会社ディスコ Grinding method of sapphire substrate
CN118617224A (en) * 2024-08-10 2024-09-10 华海清科股份有限公司 Processing device, method and wafer thinning equipment for wafer grinding

Also Published As

Publication number Publication date
JPH09199378A (en) 1997-07-31

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