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JPH0467650A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0467650A
JPH0467650A JP18100290A JP18100290A JPH0467650A JP H0467650 A JPH0467650 A JP H0467650A JP 18100290 A JP18100290 A JP 18100290A JP 18100290 A JP18100290 A JP 18100290A JP H0467650 A JPH0467650 A JP H0467650A
Authority
JP
Japan
Prior art keywords
groove
scribe line
protective film
etching
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18100290A
Other languages
Japanese (ja)
Other versions
JP2644069B2 (en
Inventor
Yoshiaki Miyawaki
宮脇 良誠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP18100290A priority Critical patent/JP2644069B2/en
Publication of JPH0467650A publication Critical patent/JPH0467650A/en
Application granted granted Critical
Publication of JP2644069B2 publication Critical patent/JP2644069B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Dicing (AREA)

Abstract

PURPOSE:To reduce the cuttings of a semiconductor substrate and to prevent cracks from occurring in the substrate around a chip region by a method wherein a groove is provided to a wafer along a scribe line provided around a semiconductor chip through an isotropic etching, and another groove is provided to the former groove through an anisotropic etching. CONSTITUTION:A protective film 4 is formed on the whole surface of a wafer provided with a scribe line 2 of shallow groove formed around a semiconductor chip region through a diffusion process. The protective film 4 formed on the scribe line 2 is so removed through etching as to leave a protective film 4a unremoved on the surface of the semiconductor chip region. Using the protective film 4a as a mask, a groove 5 is formed through an isotropic etching. By this setup, a scribe line 2a composed of the shallow groove formed through a diffusion process and the groove 5 formed through an isotropic etching is provided. Using the protective film 4a as a mask again, a groove 6 is provided through an anisotropic etching. By these processes, a scribe line 2b composed of the shallow groove formed through a diffusion process, the groove 5 formed through an isotropic etching, and the groove 6 formed through an anisotropic etching is formed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特にダイシング
に供するウェハ状態の半導体装置に関する製造方法にお
ける半導体チップ領域表面およびスクライブラインの形
状の製造方法に関する。
Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing the shape of a semiconductor chip region surface and scribe line in a manufacturing method of a semiconductor device in a wafer state to be subjected to dicing. .

〔従来の技術〕[Conventional technology]

従来、ダイシング前段階におけるウェハ状態の半導体装
W(以後、ウェハと略称する)は、第3図に示す縦断面
図のように、単にウェハ1表面における半導体チップ領
域周辺に拡散工程により形成された浅い溝からなるスク
ライブライン2を有していた。
Conventionally, a semiconductor device W in a wafer state (hereinafter referred to as a wafer) before dicing is simply formed around a semiconductor chip region on the surface of a wafer 1 by a diffusion process, as shown in a longitudinal cross-sectional view in FIG. It had a scribe line 2 consisting of a shallow groove.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述したウェハ1に対して、例えばダイヤモンドブレー
ド3によりダイシングを行なう場合、半導体装置を構成
する半導体基板のくずが発生しやすく半導体チップ領域
の表面を損傷したり、半導体チップ領域周辺近傍におけ
る半導体基板のクラックを生じやすいという欠点があっ
た。
When dicing the above-mentioned wafer 1 using, for example, the diamond blade 3, chips of the semiconductor substrate constituting the semiconductor device are likely to be generated, damaging the surface of the semiconductor chip region, or damaging the semiconductor substrate near the periphery of the semiconductor chip region. It had the disadvantage of being prone to cracking.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体装置の製造方法は、 半導体チップ領域周辺のスクライブラインに、等方性エ
ツチングによる溝を形成する工程と、スクライブライン
に、異方性エツチングによる溝を形成する工程と、 を有している。
The method for manufacturing a semiconductor device of the present invention includes the steps of: forming a groove by isotropic etching in a scribe line around a semiconductor chip region; and forming a groove by anisotropic etching in a scribe line. ing.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図(a)〜(d)は、本発明の一実施例を説明する
ための工程順の縦断面図である。
FIGS. 1(a) to 1(d) are vertical cross-sectional views in order of steps for explaining one embodiment of the present invention.

まず、第1図(a)に示すように、半導体チップ領域周
辺に拡散工程により形成された浅い溝からなるスクライ
ブライン2を有するウェハ1の全面に、保護膜4を塗布
形成する。
First, as shown in FIG. 1(a), a protective film 4 is coated on the entire surface of a wafer 1 having a scribe line 2 consisting of a shallow groove formed by a diffusion process around a semiconductor chip region.

次に、第1図(b)に示すように、スクライブライン2
上の保護膜4をエツチング除去し、半導体チップ領域の
表面に保護膜4aを残す。
Next, as shown in FIG. 1(b), the scribe line 2
The upper protective film 4 is removed by etching, leaving the protective film 4a on the surface of the semiconductor chip region.

続いて、第1図(C)に示すように、保護膜4aをマス
クに用い、等方性エツチングにより溝5を形成する。こ
れにより、拡散工程により形成された浅い溝、並びに等
方性エツチングによる溝5からなるスクライブライン2
aが形成される。なお、等方性エツチングは、ウェット
エツチングもしくは等方性プラズマエツチングが好まし
い。
Subsequently, as shown in FIG. 1C, grooves 5 are formed by isotropic etching using the protective film 4a as a mask. As a result, a scribe line 2 consisting of a shallow groove formed by the diffusion process and a groove 5 formed by isotropic etching is formed.
a is formed. Note that the isotropic etching is preferably wet etching or isotropic plasma etching.

引き続いて、第1図(d)に示すように、再び保護膜4
aをマスクに用い、異方性エツチングにより渭6を形成
する。これにより、拡散工程により形成された浅い溝9
等方性エツチングによる漬5、並びに異方性エツチング
による7116からなるスクライブライン2bが形成さ
れる。なお、異方性エツチングとしては、例えば反応性
イオンエツチング(RIE)を用いる。
Subsequently, as shown in FIG. 1(d), the protective film 4 is applied again.
Using a as a mask, the edge 6 is formed by anisotropic etching. As a result, the shallow groove 9 formed by the diffusion process
A scribe line 2b is formed by dipping 5 by isotropic etching and 7116 by anisotropic etching. Note that as the anisotropic etching, for example, reactive ion etching (RIE) is used.

第2図に示す縦断面図は、本実施例により得られた半導
体装置に対し、ダイシングに適用し、たときの図である
。スクライブライン2bにおいてダイヤモンドグレード
3は、図示したように、7115、渭6により形成され
た深い溝によりガイドされることになる。
The vertical cross-sectional view shown in FIG. 2 is a view when dicing is applied to the semiconductor device obtained in this example. In the scribe line 2b, the diamond grade 3 is guided by the deep groove formed by the grooves 7115 and 6, as shown.

ダイシング後、保護膜4aは除去され、続いて半導体チ
ップのプレイキングが行なわれる。
After dicing, the protective film 4a is removed, and then the semiconductor chip is pre-king.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、ダイシングに供するウェ
ハ状態の半導体装置の製造方法において、半導体チップ
領域の表面を保護膜で覆い、半導体チップ領域周辺のス
クライブラインには前記の保護膜をマスクに用いて等方
性、および異方性エツチングを行ない、スクライブライ
ンの部分に深い溝を形成している。
As described above, the present invention provides a method for manufacturing a semiconductor device in a wafer state to be subjected to dicing, in which the surface of a semiconductor chip region is covered with a protective film, and the protective film is used as a mask for scribe lines around the semiconductor chip region. Then, isotropic and anisotropic etching is performed to form deep grooves at the scribe line portions.

このため、ダイシングの時点で、ダイヤモンドグレード
が深い溝にガイドされるため、半導体装置を構成する半
導体基板のくずの発生、および半導体チップ領域周辺近
傍における半導体基板のクラックの発生は低減する。ま
た、よしんばくずが発生しても、半導体チップ領域表面
は保護膜により覆われているため、これによる半導体チ
ップ領域表面の損傷は生じない。
Therefore, at the time of dicing, the diamond grade is guided into the deep grooves, which reduces the generation of debris in the semiconductor substrate constituting the semiconductor device and the generation of cracks in the semiconductor substrate near the periphery of the semiconductor chip region. Further, even if dust particles are generated, the surface of the semiconductor chip region is covered with a protective film, so that the surface of the semiconductor chip region is not damaged by this dust.

第3図は従来の技術を説明するための縦断面図である。FIG. 3 is a longitudinal sectional view for explaining the conventional technique.

1・・・ウェハ、2.2a、2b・・・スクライブライ
ン、3・・・ダイヤモンドグレード、4,4a・・・保
護膜、5.6・・・溝。
DESCRIPTION OF SYMBOLS 1... Wafer, 2.2a, 2b... Scribe line, 3... Diamond grade, 4, 4a... Protective film, 5.6... Groove.

Claims (1)

【特許請求の範囲】  ウェハ状態における半導体装置の製造方法において、 半導体チップ領域の表面に保護膜を形成する工程と、 前記半導体チップ領域周辺のスクライブラインに、等方
性エッチングによる溝を形成する工程と、 前記スクライブラインに、異方性エッチングによる溝を
形成する工程と、 を有することを特徴とする半導体装置の製造方法。
[Claims] A method for manufacturing a semiconductor device in a wafer state, comprising: forming a protective film on the surface of a semiconductor chip region; and forming a groove by isotropic etching in a scribe line around the semiconductor chip region. A method for manufacturing a semiconductor device, comprising the steps of: forming a groove in the scribe line by anisotropic etching.
JP18100290A 1990-07-09 1990-07-09 Method for manufacturing semiconductor device Expired - Lifetime JP2644069B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18100290A JP2644069B2 (en) 1990-07-09 1990-07-09 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18100290A JP2644069B2 (en) 1990-07-09 1990-07-09 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH0467650A true JPH0467650A (en) 1992-03-03
JP2644069B2 JP2644069B2 (en) 1997-08-25

Family

ID=16093019

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18100290A Expired - Lifetime JP2644069B2 (en) 1990-07-09 1990-07-09 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2644069B2 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001044141A (en) * 1999-07-30 2001-02-16 Nippon Sheet Glass Co Ltd Method for cutting semiconductor substrate
EP1394851A2 (en) * 2002-09-02 2004-03-03 Shinko Electric Industries Co. Ltd. Semiconductor chip and fabrication method thereof
WO2005034214A3 (en) * 2003-09-30 2005-06-16 Intel Corp Protective layer during scribing
US6974726B2 (en) 2003-12-30 2005-12-13 Intel Corporation Silicon wafer with soluble protective coating
JP2016096320A (en) * 2014-11-06 2016-05-26 富士ゼロックス株式会社 Semiconductor chip manufacturing method
US9589812B2 (en) 2014-11-06 2017-03-07 Fuji Xerox Co., Ltd. Fabrication method of semiconductor piece
CN108511514A (en) * 2017-02-28 2018-09-07 英飞凌科技奥地利有限公司 The semiconductor wafer scribing crackle carried out using chip periphery groove is prevented

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001044141A (en) * 1999-07-30 2001-02-16 Nippon Sheet Glass Co Ltd Method for cutting semiconductor substrate
JP4581158B2 (en) * 1999-07-30 2010-11-17 富士ゼロックス株式会社 Semiconductor substrate cutting method
EP1394851A2 (en) * 2002-09-02 2004-03-03 Shinko Electric Industries Co. Ltd. Semiconductor chip and fabrication method thereof
US7052975B2 (en) 2002-09-02 2006-05-30 Shinko Electric Industries Co., Ltd. Semiconductor chip and fabrication method thereof
WO2005034214A3 (en) * 2003-09-30 2005-06-16 Intel Corp Protective layer during scribing
US7265032B2 (en) 2003-09-30 2007-09-04 Intel Corporation Protective layer during scribing
US6974726B2 (en) 2003-12-30 2005-12-13 Intel Corporation Silicon wafer with soluble protective coating
JP2016096320A (en) * 2014-11-06 2016-05-26 富士ゼロックス株式会社 Semiconductor chip manufacturing method
JP2016096325A (en) * 2014-11-06 2016-05-26 富士ゼロックス株式会社 Semiconductor chip manufacturing method
US9589812B2 (en) 2014-11-06 2017-03-07 Fuji Xerox Co., Ltd. Fabrication method of semiconductor piece
CN108511514A (en) * 2017-02-28 2018-09-07 英飞凌科技奥地利有限公司 The semiconductor wafer scribing crackle carried out using chip periphery groove is prevented

Also Published As

Publication number Publication date
JP2644069B2 (en) 1997-08-25

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