JP2705980B2 - Scanning line number conversion image display device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device using a matrix display panel such as a liquid crystal panel, and more particularly, to an image display device having a certain first number of scanning lines. A matrix display panel having a sufficient number of pixels to display a video signal is provided, and a video signal having a second scanning line number larger than the first scanning line number is to be displayed on the matrix display panel. In this case, the present invention relates to a scanning line number conversion image display device capable of reducing the number of scanning lines by thinning out the scanning lines from the second number of scanning lines and enabling display.

[Conventional technology]

There are various color TV systems, NTSC system,
The PAL system and the SECAM system are the mainstream in the world. In addition to these systems, high-definition high-vision systems have also been experimented, and color television systems have become increasingly diverse.

Generally, in order to reproduce and display a television signal as a normal image on a matrix display panel, the television signal is processed in accordance with each system, and at the same time, a matrix display panel having the number of pixels corresponding to the number of scanning lines in each system is used. There is a need.

That is, a matrix display panel in which the number of pixels is matched to the number of scanning lines of a certain method cannot be used as it is for image display of another method with a different number of scanning lines, and is usually used.

On the other hand, in Japanese Patent Application Laid-Open No. 63-169884, a horizontal scanning line is controlled by controlling a clock of a vertical shift register of a vertical scanning circuit using an NTSC matrix panel having 220 pixels in the vertical direction. Is thinned out at a ratio of one to five lines, and P having 275 horizontal scanning lines per field is used.
It discloses a technology that enables the display of an AL-type Delebi image. Further, in order to provide a natural PAL image, in the above-described known example, the position of one thinned horizontal scanning line can be changed between the first field and the second field.

[Problems to be solved by the invention]

When the thinning position matches in the first field and the second field, there is a problem that a horizontal line corresponding to the thinning position disappears from the display image.

FIG. 13 is an explanatory diagram showing the relationship between the panel line number of the liquid crystal panel 18 and the write signal scanning line number in one field before and after thinning. That is, what was as shown in FIG.
As shown in FIG. 5B, when the write scan line number 6 is thinned out in the first field and the second field, one screen (one frame) is composed of the first field and the second field. The line number 6 is not displayed on the screen at all. For example, the horizontal line on this line disappears.
For this reason, in the above-mentioned known example, an operation of changing the thinning position between the first field and the second field is performed.

However, in this case, since the position of the displayed scanning line is different between the first field and the second field, a problem arises that the horizontal line looks thick.

FIG. 14 is a diagram for explaining this, and shows the relationship between the panel line numbers of the liquid crystal panel 18 and the write scan line numbers when the positions of the thinned scan lines are changed between the first field and the second field. FIG. That is, the fourteenth
In the first field of FIG.
Are thinned out, and the write signal scanning line numbers are 3, 4, and 5 in the panema line numbers 3, 4, and 5.

On the other hand, in the second field of FIG. 14 (b), since the write signal scanning line number 3 is thinned out, the write signal scanning line numbers are 4, 5, and 6 in the panel line numbers 3, 4, and 5. For example, if there is a horizontal line signal only in the write signal scanning line number 4, the actual display looks thick over two lines by that of the first field and that of the second field.

It is an object of the present invention to provide a scanning line number conversion image display device capable of obtaining a relatively natural image by performing thinning-out in which discontinuity of the image is inconspicuous.

[Means for solving the problem]

The object is not to completely thin out the signal of one scanning line, but to half thin out the signals of two vertically adjacent scanning lines respectively to form the remaining one scanning line. This is achieved by thinning out one scanning line.

FIG. 19 is a conceptual diagram showing a basic configuration of means for solving the problem.

In the figure, the upper sample hold circuit SH (U)
Suppose that one horizontal scanning line is composed of eight pixel data of 1 to 8; first pixel data, third pixel data, fifth pixel data,
The sample pixel data can be sampled and held.

Then, the lower sample hold circuit SH (L) outputs the second pixel data, the fourth pixel data, the sixth pixel data, the eighth pixel data of the eight pixel data of one horizontal scanning line, Can be sampled and held.

One scanning electrode (A) from the vertical scanning circuit VS and signal electrodes from the upper sample and hold circuit SH (U),
,, Each intersection and the lower sample and hold circuit
○ at each intersection with the signal electrode from SH (L)
Are arranged to form a one-line matrix display device M composed of eight pixels surrounded by a broken line.

The upper horizontal shift register SR (U) is for taking in image data given via the signal path K one pixel at a time into the sample-and-hold circuit SH (U) by being supplied with a clock. Horizontal shift register SR
(L) is provided with a signal path K by being supplied with a clock.
Is to take in the image data given via the sample and hold circuit SH (L) one pixel at a time.

[Action]

The circuit operation will be described with reference to FIG. First, the operation in the case where the scanning lines are not thinned will be described. When the eight pixel data belonging to one horizontal scanning line are supplied from the signal path K, the pixels among the eight pixel data belonging to the same horizontal scanning line are sampled and held.
SH (U), and the pixels,... Are taken into the sample and hold circuit SH (L). After that, if one scan electrode (a) from the vertical scan circuit VS is driven,
Eight pixel data belonging to one horizontal scanning line input from the signal path K can be displayed on a one-line matrix display device M including eight pixels surrounded by a broken line.

Next, an operation in the case where one scanning line is thinned out of two scanning lines and displayed is described.

When the eight pixel data belonging to the first horizontal scanning line are supplied from the signal path K, the pixels, among the eight pixel data belonging to the horizontal scanning line, are supplied to the sample-and-hold circuit SH (U). Capture and discard other pixels. Next, eight pixel data belonging to the second horizontal scanning line are supplied from the signal path K, and among the eight pixel data belonging to the horizontal scanning line, pixels,.
Is taken into the sample and hold circuit SH (L), and other pixels are discarded. And under such a condition, the vertical scanning circuit
When one scanning electrode (A) from VS is driven, a one-line matrix display device M composed of eight pixels surrounded by a broken line
, The pixels in the eight pixel data belonging to the first horizontal scanning line input from the signal path K, and the pixels in the eight pixel data belonging to the second horizontal scanning line,. , And can be displayed. That is,
This means that the first and second horizontal scanning lines are thinned to one and displayed.

As described above, since it is almost the same as averaging two horizontal scanning lines vertically adjacent to each other, one horizontal scanning line will not be completely lost, and discontinuity of an image will not occur. Be lost. Further, in the first field and the second field, the horizontal scanning lines can be displayed at the same position.
A natural thinned-out image can be displayed.

〔Example〕

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an embodiment of a scanning line number conversion image display apparatus according to the present invention. FIG. 1 shows that the number of vertical pixels is reduced by thinning out one PAL image (hereinafter, also simply referred to as PAL image) having 287 effective display scanning lines in one field into six images.
FIG. 2 is a block diagram showing a device for reproducing the PAL image on a liquid crystal panel 240.

The block diagram shown in FIG. 1 shows a signal circuit 7, horizontal scanning circuits 14-1, 14-2, and a vertical scanning circuit (vertical shift register).
15, is composed of a liquid crystal panel 18.

Further, the signal circuit 7 includes a video signal (video) input terminal 1, a sync separation circuit 2, a control circuit 3, a video signal processing circuit 4, a polarity switching circuit 5, and a thinning circuit 6. Reference numerals 1 and 14-2 are arranged above and below the liquid crystal panel 18, and the horizontal shift registers 8-1 and 8-2, their shift clocks, input terminals 11-1 and 11-2 for data signals, etc., and a sample hold circuit 9-1. , 9-2 and their three primary color RGB video signal input terminals 13-1 and 13-2, n buffer amplifiers 10-1 and 10-2 for outputting a sample and hold signal, and their output control OE terminals 12-1 , 12-2.

The liquid crystal panel 18 is a horizontal 2n arranged vertically
(Upper n, lower n) horizontal signal electrodes 16-1, 16-
2. m × 2n thin-film pixel transistors (TF) whose drain and gate are respectively selected by m vertical scanning electrodes 17
T) 19, and a liquid crystal pixel 20 connected to the source of each pixel transistor.

 The operation of the circuit shown in FIG. 1 is as follows.

A horizontal / vertical synchronizing signal is separated in a sync separation circuit 2 from a PAL video signal input to an input terminal 1. Based on the horizontal / vertical synchronization signals, the control circuit 3 forms control signals necessary for driving the horizontal scanning circuits 14-1 and 14-2, the vertical scanning circuit 15, and the polarity switching circuit 5.

On the other hand, in the video signal processing circuit 4, the input PA
The L video signal is processed to form an RGB primary color signal. In the case of a black and white video signal instead of a color video signal, the video signal is a luminance signal, which is the same.

After the polarity of the video signal is switched at a fixed period by the polarity switching circuit 5, the video signal is applied to the sample and hold input terminals 13-1 and 13-2 of the horizontal scanning circuits 14-1 and 14-2. In the horizontal scanning circuits 14-1 and 14-2, the horizontal shift registers 8-1 and 8-2 operate based on the signals input to the input terminals 11-1 and 11-2 via the thinning circuit 6, and Shift register 8-1,8
-2 sample-and-hold circuits 9-1 and 9-2 according to the output of
Sample the image signals applied to the terminals 13-1 and 13-2, and simultaneously hold the data for a predetermined period.

After the sampling of the image signal for one line (one horizontal scanning line) is completed, the outputs of the sample-and-hold circuits 9-1 and 9-2 become the inputs of the buffer amplifiers 10-1 and 10-2, and the buffer amplifiers 10-1 and 10-2. The output of 10-2 is connected to its control terminals 12-1, 12-
2 is applied to the scan electrodes 16-1 and 16-2 of the liquid crystal panel 18 in accordance with the OE signal (Output / Enable signal) applied to the liquid crystal panel 18.

On the other hand, a vertical scanning circuit 15 composed of a shift register
Then, the m scanning electrodes 17 of the liquid crystal panel 18 are sequentially selected and driven based on a signal obtained by, for example, thinning out a clock from the control circuit 3 through the thinning circuit 6. When the scan electrode 17-i in the i-th row is driven, 2n transistors (19-i, 1) to (1−1) in the horizontal direction having a gate connected to the scan electrode 17-i.
9-i, 2n) are turned on all at once. At this time, buffer amplifier 1
In synchronization with the OE signals applied to the control terminals 12-1 and 12-2 of the 0-1 and 10-2, the image signals sampled and held by the sample and hold circuits 9-1 and 9-2 are output and turned on. The sampling image signal is written to the liquid crystal pixels (20-i, 1) to (20-i, 2n) via the pixel transistors (19-i, 1) to (19-i, 2n) in the state. That is, i of the liquid crystal panel 18
Image information is written to the second line.

Hereinafter, the operation of the thinning circuit 6 in FIG. 1 which is an embodiment of the present invention will be described in detail.

FIG. 2 shows a waveform diagram of main signals necessary for the operation of the circuit of FIG. The signals shown in FIG. 2 are the horizontal synchronizing signal Hsync applied to the control circuit 3, the image signal R (red) applied to the terminal 13, the start pulse STH1 of the horizontal shift register 8-1 applied to the terminal 11-1, and the like. Shift clock (equivalent to sampling clock) CPH1, terminal 11
Pulse STH2 of the horizontal shift register 8-2 and the shift clock CPH2 added to the horizontal shift register 8-2, and the vertical scanning circuit
Reference numeral 15 denotes a start pulse STV, its shift clock CPV, and a control signal OE for the buffer amplifiers 10-1 and 10-2 applied to the terminal 12.

The vertical scanning is performed by the vertical shift clock CPV at the time of input of the start pulse STV of the shift register of the vertical scanning circuit 15.
Start based on the rising edge of. In FIG. 2, the same number is assigned to the pulse of each related signal. That is, the signal related to the first horizontal scanning cycle is number 1, the signal related to the second horizontal scanning cycle is number 2, and so on.

That is, the scanning panel is output from the first stage of the vertical shift register 15 at the rise of the pulse 1 of the CPV, and the first scanning electrode 17-1 of the liquid crystal panel 18 is driven.

On the other hand, the image signal R is sampled and held 9 (9-1, 9) by the pulses of STH1 and STH2 which are synchronized with the pulse 1 of Hsync about one horizontal cycle before the pulse 1 of CPV.
-2). This sampling data is Hsync1
The signal is output from the buffer amplifiers 10-1 and 10-2 by the control signal OE which rises after about one horizontal scanning cycle, and is written to the first line of the liquid crystal panel 18. The waveform of the signal electrode 16-1,1 is the waveform 16-1,1 in FIG. 2, and the waveform of the signal electrode 16-2,1 is the waveform 16-2,1 in FIG.

In the thinning circuit 6 shown in FIG. 1, for example, as shown in FIG. 2, STH1 thins out the pulse 6 and the CPV, OE thins out the pulse 5 and thereafter at intervals of one every six. (Thinned out pulses are shown by dashed lines). At this time, since the pulse 6 of the STH1 has been thinned out, the sample and hold circuit 9-1 does not sample the image signal 6, and the data of the image signal R 5 is held.

On the other hand, in the sample hold circuit 9-2, STH2
6 of the image signal R is sampled by the pulse 6 of. Further, at the time corresponding to the pulse 5 of the CPV, the vertical shift register 15 does not operate, and remains stopped at the state of the pulse 4 of the CPV. The signal waveform applied to the scanning electrode 17 is a sequential selection waveform shown in 17-1, 17-2, 17-3, 17-4, and 17-5 in FIG. That is, the state where the fourth line of the liquid crystal panel 18 is selected is continued for the period of CPV5.

At this time, since the pulse 5 of the control signal OE is also stopped at the same time, there is no change in the contents of the pixels in the fourth line, and the image signal R 4 is continued. And the fifth pulse by CPV pulse
After the line is selected, the signal electrode
16-1 outputs 5 data of the image signal R, and the signal electrode
The data of the image signal R is output to 16-2. Therefore, as the pixels on the fifth line of the liquid crystal panel 18, the signals 5 and 6 of the image signals R are alternately written and simultaneously displayed.

FIG. 3 shows the relationship between the scanning lines of the write signal displayed on the liquid crystal panel 18 by the thinning circuit 6 and the line numbers on the liquid crystal panel 18.

FIG. 3A shows the relationship in an odd field display organization. The liquid crystal panel 18 has 240 pixels in the vertical direction, and can write 240 scanning lines. Numbers are assigned to the writable scanning lines on the liquid crystal panel 18, and the numbers are described on the left side of FIG. 3A as panel line numbers. On the other hand, the scanning line numbers of the actually written image signals are shown on the liquid crystal panel 18 in FIG.

The thinning circuit 6 thins out the start pulse STH1, the vertical shift clock CPV, and the horizontal sampling output control signal OE of the horizontal shift register 8-1 according to the description of the waveform diagram of FIG. As shown in line number 5, image signals for two scanning lines are alternately displayed in a horizontal direction on one panel line, in other words, an averaged signal of two adjacent scanning lines. Is displayed, and image signals are written at a rate of 5 out of 6 lines.

As a result, as shown in FIG. 3A, an image signal in which one scanning line is thinned out every six lines is written on the liquid crystal panel 18, so that the liquid crystal panel 18 having 240 lines is formed. , The image of the odd field composed of 287 scanning lines from the first to 287 lines is displayed in a vertically reduced state.

Similarly, in the even field shown in FIG. 3B, the screen of the even field which is originally composed of 287 scanning lines from the 313th line to the 599th line is reduced on the liquid crystal panel 18 in the vertical direction. Is displayed.

FIG. 4 shows a thinning relation aiming at a more natural display than the thinning relation of FIG. In FIG. 3, the order of the two write signal scanning line numbers written on one panel line of the liquid crystal panel 18 is such that the younger numbers are on the left in both the odd and even fields. That is, 1
In a frame, image signals at the same position are thinned out. On the other hand, in FIG. 4, the above-mentioned order is changed between the odd field and the even field so that the thinning is uniform.

However, in this case, it is necessary to thin out STH2 instead of the start pulse STH1 in FIG. That is, when one of the start pulses STH1 to STH2 is thinned, the other start pulse is not thinned.

Therefore, according to the invention shown in FIG. 4, the discontinuity of the image is not noticeable, and the PAL is applied to the liquid crystal panel 18 having the aspect ratio of 4: 3.
Images can be displayed more naturally with the same aspect ratio of 4: 3. Therefore, the effect of the present invention is clear.

FIG. 5 shows a specific circuit configuration example of the thinning circuit 6 in FIG. The circuit shown in FIG. 5 is roughly divided into two blocks. One is a thinning pulse generation circuit 21 and the other is a gate circuit 37.

The thinning pulse generation circuit 21 includes a counter 25 and timing adjustment circuits 26, 27, and 28. Counter 25 is connected to terminal 23
Based on the STV (start pulse V) input to
For example, every six Hsyncs (horizontal synchronization signals) input to the terminal 24 are counted. That is, the counter 25 is set to Hsync6
A pulse is generated for each unit.

Based on this pulse, the timing adjustment circuit 26 generates a negative pulse covering the pulse 5 (dashed line) of the CPV in FIG. 2, and the timing adjustment circuit 27 generates a negative pulse covering the pulse 5 (dashed line) of the OE. A pulse is generated, and the timing adjustment circuit 28 generates a positive pulse covering the pulse 6 (broken line) of STH1.

The timing adjustment circuit is a delay circuit as shown in FIG.
57 and monostable multivibrator 58.
After a pulse input to 59 is delayed by a delay circuit 57 for a fixed time, a pulse having a fixed width is formed by a monostable multivibrator 58 and output from a terminal 60.

The gate circuit 37 includes four AND circuits, two NAND circuits, and one inverter circuit. The AND 33 gates the CPV input to the terminal 30 with the thinning pulse from the timing adjustment circuit 26. Further, since the thinning pulse from the timing adjustment circuit 26 has a negative polarity, it is input to the terminal 30.
The CPV pulses are thinned out at a rate of one out of six and output from the terminal 38.

Similarly, in the AND34, the OE pulse input to the terminal 31 is also thinned out at a rate of one out of every six in the AND34, and
Output from 9. In NAND57, the field discrimination signal FD
In the odd field or the even field, the pulse of the positive polarity of the timing adjustment circuit 28 is output with the negative polarity.

In the AND 35, in accordance with this pulse, the STH pulse input to the terminal 32 is thinned out at a rate of one in six, and
Output as TH1. Similarly, in the NAND 58, based on the output of the inverter 29 to which the field discrimination signal FD is input, the positive pulse of the timing adjustment circuit 28 is output in a field different from that of the NAND 57, and is output.

In the AND 36, in accordance with this pulse, the STH pulse input to the terminal 32 is thinned out at a rate of one out of six, and the S
Output as TH2. The field discrimination signal FD is
Formed from the vertical sync signal, the sync is twice the vertical sync signal.

FIG. 7 shows a second embodiment of the present invention. The difference from the first embodiment shown in FIG. 1 is that an average of signals of two rows in a horizontal scanning period is averaged to be one row. For this purpose, as shown in FIG. 7, the circuit configuration is such that a circuit 44 surrounded by a broken line is inserted between the video signal processing circuit 4 and the polarity switching 5.

Within the broken line 44, there is an analog switch 43. By switching this switch, an output signal 45 of the video signal processing circuit 4 is output.
Or the output 49 of the averaging circuit is output. Switching of the analog switch 43 is performed by the control signal 51 of the thinning circuit 106.

The averaging circuit has the configuration shown in FIG. Delay circuit
48 has a delay amount for one horizontal cycle. 46 is an adder, 47 is 6d
B attenuator (voltage 1/2). That is, the averaging circuit 49
Is the signal average value for two rows in the horizontal scanning cycle.

The operation of FIG. 7 will be described with reference to the waveform diagram of FIG. However, the sync separation circuit 2, the control circuit 3, the video signal processing circuit (video chroma circuit) 4, and the polarity switching circuit 5 are the same as those of the first embodiment, and therefore will not be described here.

The signals switched by the analog switch 43 are the output 45 of the video signal processing circuit 4 and the output 49 of the averaging circuit. 49 is the average value of two rows as described above,
In order to express this, it is written in the waveform diagram as (1 + 2), (2 + 3),.... The signal for controlling the switching of the analog switch is the output 51 of the thinning circuit 106. When the period 51 is positive, the input 50 of the polarity switching circuit 5 is the output signal 45 of the video signal processing circuit 4, and when the period 51 is negative, the input 50 is the output 49 of the averaging circuit 42. .

That is, when the control signal 51 has a negative polarity, for example, an averaged signal of (5 + 6) is selected and sampled and held by STH6. The sampled and held data is synchronized with the pulse 6 of the OE,
And written on the liquid crystal panel 118.

Of course, in the vertical scanning circuit 15, as in the first embodiment,
The control is performed by thinning out the pulse 5 of the CPV. Further, by thinning out the OE pulse 5, the writing of the image signal 5 sampled and held by the STH pulse 5 is prohibited. Therefore, the signals 116 written to the liquid crystal panel are 1, 2, 3, 4, (5 + 6), 7,.

FIG. 10 shows a third embodiment of the present invention. In Figure 10,
In some rows of the liquid crystal panel 218, a feature is that two gate lines exist for one row of pixels in the horizontal direction. Here, the pixel 55 in FIG. 10 may be considered to be equivalent to the combination of the pixel transistor 19 and the liquid crystal pixel 20 in FIG.

The two gate lines allocated to one row are, for example, 55-
The gate lines 217-5 and 217-6 are arranged for the pixels in five rows. That is, 55−5,1,5 of the pixels in one row
5-5, 3, 55-5, (2n-1) are connected to the gate line 217-5, and the remaining pixels 55-5, 2, 55-5, 4, 55-5, (2n) are gated. Connected to line 217-6. In the vertical scanning circuit 215 as well, a shift register is constituted by the same number of flip-flops 53 as the number of gate lines, and the gate 217 is driven by the buffer amplifier 52.

The gate lines 217-5 and 217-6 are determined by the switch 56 to be simultaneously selected or sequentially selected. This is a flip-flop
The difference is whether 53-4 and 53-5 receive the data 54-4 of 53-4 simultaneously or 53-4 and 53-5 sequentially.

Therefore, when the gate lines 217-5 and 217-6 are selected at the same time, a television signal type display having the same number of horizontal scanning lines as the number of horizontal pixels of the liquid crystal panel 218 can be performed. When the gate lines 217-5 and 217-6 are sequentially selected, the same effect as in the first embodiment can be obtained.

In the third embodiment, thinning-out display is possible only by switching the switch 56.

FIG. 11 shows a fourth embodiment of the present invention. A feature of the fourth embodiment resides in a liquid crystal panel 318. In the third embodiment,
Although two gate lines are arranged in some rows, in the fourth embodiment, two gate lines are added in all rows. Since the arrangement of the two gate lines is as described above, it will not be described here.

In the vertical direction, one signal line is arranged for two adjacent pixels. For example, a common signal line is arranged in the columns of the pixels 55-1,1 and 55-1,2. As a result, pixel 55
Even if either −1, 1 or 55−1, 2 is damaged, the display in the first horizontal row and first vertical column is possible as long as the other is safe.

The differences from FIG. 1 are the structure of the liquid crystal panel 318, the arrangement of the horizontal scanning circuit 14, the arrangement of the vertical scanning circuit 15, and the thinning circuit. The horizontal scanning circuit 14 has one on the liquid crystal panel 318,
The vertical scanning circuit 15 is arranged on both left and right sides of the liquid crystal panel 318.

The operation of FIG. 11 will be described based on the waveform diagram of FIG. A horizontal synchronization signal Hsync, an image signal R, a start pulse STH of a horizontal shift register and its shift clock CPH,
Start pulse STV of vertical shift register, O for output control
The E signal has been described completely and will not be described here.

CPV1 is a shift clock of the vertical shift register in the vertical scanning circuit 15-1, and CPV2 is a shift clock of the vertical shift register in the vertical scanning circuit 15-2. M1 is a signal for controlling the output of the vertical scanning circuit 15-1. When M1 has a negative polarity, the output of the vertical scanning circuit 15-1 is prohibited, and no gate line is selected. Similarly, M2 is an output control signal of the vertical scanning circuit 15-2.

In order to obtain the same effect as in the first embodiment, here, CPV1
And thin out CPV2. For example, pulse 6 of FIG. 12, CPV1, CPV2
Of the gate lines 17-2, 4, 17
−2 and 5 are waveforms including the broken line in FIG. Further, a broken line portion of 17-1, 5 is represented by an M1 signal, and a 17-
Control the dashed lines 2 and 4. That is, 17-2, 4, 17-1,
5 becomes like a solid line.

At this time, first, the fourth row of the liquid crystal panel 318 is
−1,5, 17−2,4 at the same time, the signal 4 on the signal line 16
Is written. Next, the odd-numbered pixels (55-5, 1, 55-5, 3 ...) in the fifth row are selected by the gate line signals 17-1, 5 and the signal 5 of the signal line 16 is written. The even-numbered pixels (55-5, 2, 55) in the fifth row are determined by the line signals 17-2,5.
−5, 4...) Is written with the signal 6 of the signal line 16. Therefore, the effects of the present invention can be obtained.

FIG. 15 shows a fifth embodiment of the present invention. This example, as described in detail in JP-A-63-26084,
This is an example in which the present invention is applied to double-speed line sequential scanning in which video signals of one horizontal scanning cycle are sampled, and two adjacent rows of pixels are separately driven in the first and second half of the subsequent one horizontal scanning cycle. .

FIG. 15 has basically the same circuit configuration as FIG. The difference is that the signal controlled by the thinning circuit 306 is
Only the vertical scanning circuit 315 is required, and the horizontal scanning circuit 214 is not specially controlled by thinning.

A detailed block diagram of the thinning circuit 306 is shown in FIG. The basic configuration is the same as that of FIG. 5, and the timing adjustment circuits 126 and 127 are as shown in FIG. Therefore, detailed description of the circuit operation is omitted.

FIG. 16 is a diagram for explaining FIG. 15, and shows a relationship between panel line numbers and write signal scanning line numbers in the liquid crystal panel 418.

FIG. 18 is a main signal waveform diagram of FIGS. 15 and 17. In the above-described double-speed sequential scanning, in one of the first field and the second field, if no thinning is performed, a simultaneous scanning line signal is applied to two adjacent rows as shown in FIG. Written. For example, the signal of write signal scanning line number 2 is written to panel line numbers 3 and 4. In the other field, the signals of the same scanning line are written in two adjacent rows by shifting the combination of panel line numbers. For example, the signal of the writing scanning line number 2 is written to the panel line numbers 2 and 3.

In this double-speed line sequential scanning, when the thinning operation of the present invention is performed, the result is as shown in FIG. 16 (b). That is,
The signals of the write signal scanning line numbers 5 and 6 written in the panel line numbers 10 and 11 shown in FIG. 16A are thinned out, and the panel line numbers 9 and 9 of the liquid crystal panel 418 in FIG. Write signal scanning line numbers 5 and 6 are written in two rows of 10. As a result, in double-speed line sequential scanning, an average of two adjacent horizontal scanning lines can be obtained.

The thinning operation of the embodiment shown in FIG. 5 will be described based on the main signal waveform diagram shown in FIG. In double-speed line sequential scanning,
The cycle of the shift clock CPV of the vertical scanning circuit 315 in FIG.
One half of the Hsync cycle. The control signal OE is also Hsy
It has a half period of nc. Therefore, for example, the signal line 317-3 is selected by the CPV pulse 2-1 and the image signal 2-1 of the signal line 217 is applied to the pixel selected by the signal line 317-3 by the OE pulse 2-1. Written.

Similarly, the pixel selected by the signal line 317-4 has the signal line 2
Seventeen image signals 2-2 are written. That is, two lines of panel line numbers 3 and 4 of the liquid crystal panel 418 in FIG.
The signal of the write scan line number 2 is written.

Here, attention is paid to the pulses 5-2 and 6-1 of the CPV in FIG. These pulses are decimated by the decimating circuit 306 as shown by the broken lines. Therefore, the signal line 317
The output of -9 is formed by combining the solid line and the broken line. Further, by controlling the output of the vertical scanning circuit to be inhibited by setting the M signal to a negative polarity, the output of the signal line 317-9 becomes only a solid line.

At this time, the image signal of 5-1 on the signal line 217 is written to the pixel selected by the signal line 317-9 by the OE pulse 5-1. , OE
With the pulse 6-2, the image signal of the signal line 217 6-2 is written. That is, as shown in FIG. 16 (b), the image signal 5 is assigned to the panel line number 9 of the liquid crystal panel 418.
Is written, and the image signal 6 is written to the panel line number 10.

〔The invention's effect〕

As described above, according to the present invention, the number of scanning lines can be reduced without losing one of the two rows by decimating one row on average from signals of two rows in the adjacent horizontal scanning cycle. This is advantageous in that an image having a larger number of scanning lines can be naturally displayed on a display panel having a smaller number of display scanning lines in a form in which discontinuities are reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a signal waveform diagram of a main part thereof, and FIGS. 3 and 4 are panel line numbers and display image signal signals in relation to the present invention. FIG. 5 is a circuit diagram showing a specific example of a thinning circuit in FIG. 1, FIG. 6 is a block diagram showing a configuration example of a main part in FIG. 5, and FIG. FIG. 10 is a block diagram showing another embodiment of the present invention, FIG. 8 is a circuit diagram showing a specific example of the averaging circuit in FIG. 7, FIG. 9 is a signal waveform diagram of a main part in FIG. FIG. 11 is a block diagram showing another embodiment of the present invention, FIG. 12 is a signal waveform diagram of a main part in FIG. 11, and FIGS. 13 and 14 are respectively related to the embodiment of the present invention. FIG. 15 is an explanatory diagram showing a relationship between panel line numbers and scanning lines of a display image signal, and FIG. 15 shows still another embodiment of the present invention. FIG. 16 is a block diagram, FIG. 16 is an explanatory diagram showing a relationship between panel line numbers and scanning lines of a display image signal in relation to the embodiment of the present invention, and FIG. 17 is a configuration example of a main part in FIG. FIG. 18 is a signal waveform diagram of a main part in FIG. 15, and FIG. 19 is a conceptual diagram showing a basic configuration of means for solving the problem of the present invention. Description of symbols 1 ... video input terminal, 2 ... synchronization separation circuit, 3 ... control circuit, 4 ... video signal processing circuit, 5 ... polarity switching circuit,
6 thinning circuit, 14 horizontal scanning circuit, 15 vertical scanning circuit,
18… LCD panel, 43,56… Switch, 48,57… Delay circuit,
58… Monostable multivibrator

Claims (4)

(57) [Claims] 1. A matrix display panel having a number of pixels sufficient to display a video signal having a first number of scanning lines, the number of second scanning lines being larger than the first number of scanning lines. When a video signal having the following is displayed on the matrix display panel, the number of scanning lines is reduced and displayed by thinning out the scanning lines from the second number of scanning lines. In the device, a plurality of scanning electrodes (17-1 to 17-m) extending in one direction and a plurality of signal electrodes (16-17) extending in a direction intersecting the one direction are provided.
1,1 to 16-1, n: 16-2,1 to 16-2, n) and display elements (20-1,1 to 2
0-m, 2n), and the plurality of signal electrodes (16-1, 1 to 16-1, n: 16-2, 1 to 16-)
2, n) is divided into a plurality of sets, and a horizontal scanning circuit (14
-1, 14-2), a vertical scanning circuit (15) connected to the plurality of scanning electrodes, and a video signal having the first number of scanning lines.
A drive signal for driving the vertical scanning circuit (15) once after capturing and holding image information belonging to the same scanning line in each sample and hold circuit of the plurality of sets of horizontal scanning circuits (14-1, 14-2). To display video signals having a number of second scanning lines greater than the number of first scanning lines, each of the plurality of sets of horizontal scanning circuits (14-1, 14-2) And a drive signal supply circuit (6) for supplying a drive signal for driving the vertical scanning circuit (15) once after capturing and holding image information belonging to different scanning lines in the sample and hold circuit. A scanning line number conversion image display device characterized by the above-mentioned. 2. A matrix display panel comprising: a plurality of scanning electrodes extending in one direction; and a plurality of signal electrodes extending in a direction intersecting the one direction, and a display element arranged and connected at the intersection thereof. In a matrix display device including a vertical scanning circuit connected to an electrode and a horizontal scanning circuit connected to the signal electrode, the display elements in one direction and one row in the matrix display panel are all in the same single scan. A row connected to the electrodes;
A row in which display elements constituting one row and one row are alternately connected to two adjacent scanning electrodes is mixed and positioned on the matrix display panel, and the adjacent ones are arranged in the vertical scanning circuit. A scanning line number conversion image display device, comprising: a switching switch for simultaneously selecting and driving two scanning electrodes or sequentially selecting and driving two scanning electrodes. 3. A matrix display panel having a plurality of scanning electrodes extending in one direction and a plurality of signal electrodes extending in a direction intersecting the one direction, wherein a display element is arranged and connected at the intersection thereof, and In a matrix display device comprising: a vertical scanning circuit connected to an electrode; and a horizontal scanning circuit connected to the signal electrode, the plurality of scanning electrodes each include a first scanning electrode and a second scanning electrode. In the matrix display panel, each of the display elements constituting one row and one row is alternately connected to the adjacent pair of scan electrodes, and is constituted by a plurality of pairs of scan electrodes. A certain sequential scanning waveform is applied to the pair of scanning electrodes from the vertical scanning circuit simultaneously to one of a pair of scanning electrodes connected to the display elements constituting one row to constitute one row in one direction. Connect to display element The vertical scanning circuit is driven so that the remaining scanning electrodes of the succeeding pair are supplied with a sequential selection waveform shifted by one horizontal scanning period from the pair of scanning electrodes. A scanning line number conversion image display device, comprising: 4. A matrix display panel having a plurality of scanning electrodes extending in one direction and a plurality of signal electrodes extending in a direction intersecting the one direction, wherein a display element is arranged and connected at the intersection thereof, and In a matrix display device comprising: a vertical scanning circuit connected to an electrode; and a horizontal scanning circuit with a sample hold circuit connected to the signal electrode, the vertical scanning circuit sets the scanning electrode to a 1/2 horizontal scanning cycle. Correspondingly, sequentially driving the scanning electrodes, and sequentially driving the scanning electrodes,
A scanning line number conversion image display device controlled so as to pause twice consecutively.