JP2760785B2 - Matrix image display device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a means for reducing output voltage variation of a matrix image display device having, as pixels, display elements such as liquid crystals arranged in a matrix. 2. Description of the Related Art In a matrix image display device, when performing so-called line-sequential scanning in which all pixels in one row are simultaneously driven, a sample hold for holding a pixel image signal from sampling to driving the pixel. Circuit is required. A method of driving a pixel of a display pulse using such a sample and hold circuit is discussed in the Institute of Television Engineers of Japan, Vol. 6 (IPD75-6) (1983), pp. 29-34. [Problems to be Solved by the Invention] In the prior art, the hold voltage immediately before the sampling of the sample and hold circuit for sampling the television image signal in the horizontal effective display period is the voltage of the television image signal sampled in the previous horizontal effective display period. Therefore, there is a problem that even if the same signal voltage is sampled when the voltage is different, the voltage to be held thereafter is different and causes variation. SUMMARY OF THE INVENTION It is an object of the present invention to provide a matrix image display device in which a variation in a hold voltage immediately after sampling of a television image signal sampled during a horizontal effective display period by a sample and hold circuit is reduced. [Means for Solving the Problems] The object of the present invention is to perform a first effective sampling operation within a horizontal retrace period of an image signal after the polarity is inverted, and then display a horizontal effective display adjacent to the horizontal retrace period. This is achieved by configuring the sample and hold circuit in the matrix image display device to perform the second sampling operation within the period. [Operation] Each sample and hold circuit that samples an image signal during the horizontal effective display period samples a signal voltage of, for example, a black level in a horizontal retrace period immediately before the horizontal effective display period. As a result, the voltage of the hold capacitor of the sample-and-hold circuit immediately before the sampling of the image signal always becomes substantially the black level voltage. If the black level voltage is not sampled, even if the same image signal is sampled during the horizontal effective display period, the held voltage varies because the held voltage varies, whereas the black level voltage is Sampling reduces the variation because the hold voltage is constant. When a television image signal whose polarity is inverted every horizontal scanning cycle is used, a sample and hold circuit that samples the television image signal every horizontal scanning cycle supplies a horizontal return immediately before the horizontal effective display period for sampling the television image signal. By simultaneously sampling the black level voltage of the same polarity in the line period in advance, the voltage of the hold capacitor is compared with the case where the TV image signal of the opposite polarity is sampled after the TV image signal of the opposite polarity is sampled. , The time required to keep the error of the hold voltage with respect to the applied voltage within a predetermined error can be shortened. Alternatively, the impedance of the analog switch of the sample-and-hold circuit composed of MOS transistors and the like can be increased for the same required write time, so that the occupied area can be reduced. Embodiment An embodiment of the present invention will be described with reference to the drawings. In the following description, a driving circuit for an active matrix type image display device using a display panel having switching elements arranged in a matrix and pixels composed of liquid crystal or the like will be described, but the same applies to other driving circuits for a matrix image display device. Effects can be obtained. FIG. 1 shows a drive circuit for an active matrix type image display device according to an embodiment of the present invention. In the following description, an example in which liquid crystal is used as a display element will be described, but the operation is the same when other elements are used. 1 is a horizontal scanning shift register, 2 is an OR (OR) circuit, 3 is a level shifter,
Reference numeral 4 denotes an analog switch composed of, for example, a MOS transistor, etc., reference numerals 5 and 7 denote holding capacitors, reference numeral 6 denotes a buffer amplifier having a control terminal OE capable of setting an output to a high impedance state, reference numeral 8 denotes a vertical scanning shift register, and reference numeral 9 denotes Is a column signal electrode, 10 is a row scanning electrode, 11 is a MOS transistor, 12 is a liquid crystal cell, 13 is a liquid crystal panel, and a broken line SR portion is a shift register portion that can simultaneously select all output stages. Hereinafter, the embodiment of FIG. 1 will be described with reference to the operation waveform examples shown in FIG. The horizontal scanning shift register 1 in FIG. 1, synchronous with the horizontal synchronizing signal of the television picture signal V _1, the liquid crystal panel 1
A clock pulse φ _H corresponding to the number of horizontal pixels of 3;
A scanning start signal _DH obtained by delaying the horizontal synchronizing signal is applied. The output Q _κ of each stage of the shift register (κ = 1,2,
3 ...) is applied with the reset signal RS to the OR (OR) circuit, a signal for selecting one by each one horizontal effective display period and the horizontal blanking period of the horizontal scanning period of the television picture signal V _I P
_κ is formed and converted into a voltage level at which the analog switch 4 can be driven by the level shifter 3. Analog switch 4
Forms a sample-and-hold circuit with the hold capacitor 5, all of the sample-and-hold circuit television image signal V _I television image polarity inversion at a timing according to the reset signal RS during the horizontal blanking period in each horizontal scanning period of the Signal V
Substantially intermediate voltage of _I, for example, sampling the voltage corresponding to the black level. Continued horizontal effective display period in each sample and hold circuit samples the television image signal V _I at a timing corresponding to the pixel arrangement of the liquid crystal panel 13, and holds the signal voltage commensurate with the column signal electrodes 9 are responsible for driving the respective hold capacitor 5 I do. The held signal voltage is input to the buffer amplifier 6 with output control, and the buffer amplifier 6 with output control is operated during the period in which the output control signal OE is at “H” level during the horizontal blanking period, and the column signal electrode is operated. 9 is driven. On the other hand, the vertical scanning shift register 8 has a clock pulse φ _V of a horizontal scanning cycle (substantially the same as the horizontal scanning start signal,
Or slightly applied phase advanced pulse) and a vertical scanning start signal D _V obtained by delaying the vertical synchronizing signal, MOS transistor 11 whose gate is connected to the row scanning electrodes 10 corresponding to the horizontal scanning lines of the television Is turned on, and the signal voltage applied to the column signal electrode 9 is written in the liquid crystal cell 12 to display an image. The liquid crystal itself and MOS transistor 1
If the leak at the time of 1 cannot be ignored, a signal storage capacitor may be added to the liquid crystal drive electrode of each pixel. One electrode of all the liquid crystal cells is connected in common, and a substantially midpoint potential of the signal voltage is applied to drive the liquid crystal by AC. In Figure 2, the television picture signal V _I for AC-driving the liquid crystal is in the AC signal polarity is inverted every horizontal scanning period. Sample hold circuit television image signal V television image signal of horizontal effective display period immediately before sampling the _I V _I during the black level "H" level reset signal RS
There is input becomes the all output P _kappa "H" level of the OR circuit 2, all of the analog switch 4 is turned on. Thus, all of the hold capacitor 5, the voltage of the black level of the television picture signal V _I is written. If a reset signal of “L” level is input immediately before the subsequent horizontal effective display period starts, all outputs _Qκ of the horizontal scanning shift register 1 are at “L” level. The output _Pκ becomes “L” level, and all the analog switches 4 are turned off, thereby completing the sampling, that is, the reset operation. When the next horizontal effective display period comes,
Each sample and hold circuit sequentially samples the television image signal by the output _Qκ of each stage of the horizontal scanning shift register 1. The buffer amplifier 6 drives the column signal electrode 9 with the sampled image signal voltage during a period in which the output control signal OE is “H” in the horizontal retrace period of the next horizontal scanning cycle. Subsequently, when the output control signal OE goes to “L” level, the output of the buffer amplifier 6 goes into a high impedance state, and the signal voltage applied to the column signal electrode 9 until the buffer amplifier 6 goes to the next output state Column signal electrode 9
Is held by the hold capacitor 7 connected to the.
If the leakage of the column signal electrode 9 is small, the stray capacitance can be used as the hold capacitance 7. The signal voltage held by the hold capacitor 7 passes through the MOS transistor 11 whose gate is connected to the row scanning electrode 10 selected by the output of the vertical scanning shift register 8, and is output until the next time the buffer amplifier 6 enters the output state. The data is written to the liquid crystal cell 12 in the meantime. At the same time, the sample-hold circuit after reset operation, sampling the television picture signal V _I.
Thereafter repeated sampling and write operation of the television image signal V _I in the same manner. Thus, after a voltage corresponding to the black level of the AC television image signal V _I for polarity inverted every horizontal scanning period every sample hold circuit is sampled, sample the television image signal V _I in the horizontal effective display period Therefore, the sampling can be performed without being affected by the signal voltage sampled in the immediately preceding horizontal effective display period, and the variation in the voltage held by the hold capacitor 5 can be reduced. Further, since the sampling of the same polarity of the television image signal V _I and the black level after sampling the black level, the change of the hold voltage of the hold capacitor 5 during sampling than when sampling opposite polarities of a television image signal V _I Therefore, there is an advantage that the time required for keeping the error of the hold voltage from the applied voltage within a predetermined error can be shortened. Or MO for the same write time
Since an increase in the impedance of the analog switch 4 constituted by an S transistor or the like can be tolerated, the occupied area can be reduced. Another embodiment of the present invention is shown in FIG. Fig. 3 shows the first
This is another configuration example of the shift register portion that can simultaneously select all output stages surrounded by broken lines in the drawing. 14 is an analog switch composed of, for example, a MOS transistor or the like, and 15 is a hold capacitor that holds a signal voltage immediately before the analog switch is turned off when the analog switch is turned off.
Parasitic capacitance may be used instead. Reference numeral 16 denotes a non-inverting buffer, which is, for example, two inverters connected in cascade. Reference numerals 17 and 21 denote inverters, 18, 19 and 20 denote OR circuits, 22 and 23 denote NAND circuits, and 24 denotes an RS flip-flop constituted by NAND circuits 22 and 23. Hereinafter, the embodiment of FIG. 3 will be described with reference to the operation waveform examples shown in FIG. (FIG. 3 does not show a portion to which the television image signal V _I is applied, but FIG. 4 shows a waveform of the television image signal V _I for explanation of the operation.) sample-and-hold circuit controlled by the output P _kappa samples the television picture signal V _I during the horizontal effective display period. During the black level period of the TV image signal immediately before the horizontal effective display period, the reset signal
When RS goes to the "H" level, the output of the RS flip-flop 24 (the output of the NAND 23) RS-0 goes to the "H" level, so that the control voltage of the analog switch 14 through the OR circuits 18 and 19 becomes "H". "All levels of analog switches 14
Is turned on. At the same time, the reset signal RS that has become “H” level is input to the first-stage input terminal of the dynamic shift register through the OR circuit 20. As described above, since all the analog switches 14 are in the ON state, the "H" level of the first-stage input is transmitted to all the output stages of the dynamic shift register, so that the reset signal RS becomes "H".
It can be sampled black level of the television picture signal V _I for all of the sample-and-hold circuit controlled by the output P _kappa of the dynamic shift register during a period in which a level. When the reset signal RS becomes “L” level, an “L” level signal voltage is applied to the first-stage input terminal of the dynamic shift register. At this time, since the last stage of the dynamic shift register is at the "H" level, the output RS-0 of the RS flip-flop 24 remains at the "H" level, and all the analog switches 14 are on. . Therefore, the "L" level of the first stage input is transmitted to the last stage. When the final stage becomes "L" level, the output RS-0 of the RS flip-flop 24 becomes "L" level, so that the control voltage of the analog switch 14 becomes "L" level and all the analog switches 14 are turned off. . Each sample-and-hold circuit controlled by the output P _kappa of the dynamic shift register becomes the subsequent horizontal effective display period newly starts sampling of the television picture signal V _I. By using the embodiment shown in FIG. 3, the same effect as that of the embodiment shown in FIG. 1 can be obtained. Another embodiment of the present invention is shown in FIG. 5, and an example of the operation waveform is shown in FIG. The embodiment of FIG. 5 drives a liquid crystal panel having about 480 pixels in the vertical direction in consideration of, for example, NTSC television image display. 25 is an AND circuit, 26 is a shift matrix, and 27 is a voltage follower. Figure 1 embodiment greatly differs from the 4 strains has sample and hold circuit per column signal electrode driving circuit, the television picture signal V _I Each of the sample-and-hold circuit 2 horizontal scanning every cycle
Sampling, and sequentially switching and outputting the held signal voltage every half cycle of the horizontal scanning cycle; and
The point is that the number of stages of the shift register 8 'for vertical scanning is twice that of the shift register 8 of FIG. 1, and a clock pulse φ _V having a frequency twice the horizontal scanning frequency is applied. lcl = 3j−2; j = 1, 2, 3...), and the operation of the embodiment of FIG. 5 will be described with reference to the waveforms of FIG. In the following description, (Red, Gre, Blu, R, G, B) will be referred to as (Gre, Bl) for the drive circuit of the column signal electrodes 9-1 +1, 9-1 +2 of the l + 1, l + 2 columns.
If u, Red, G, B, R) and (Blu, Red.Gre, B, R, G) are replaced, the same operation is performed, and the description is omitted. Here, a sample-and-hold circuit including the analog switches 4Al, 4Bl, 4Cl, and 4Dl and the respective hold capacitors 5 is S / H
-A, S / H-B, S / H-C, S / H-D and to be called, the sampling operation period "W", the selection switch _{S A l, S B l,} S C l, S
A signal voltage in which _D 1 is selected and held is sent to the buffer amplifier 6, and an output period for driving the column signal electrode 9-1 is indicated by a symbol “R”. Note that, in the parentheses following the sampling period “W”, the three primary color signals Red sampled by each sample and hold circuit are shown.
(Red), Gre (Green), Blu (Blue) and RS (Black level voltage)
In addition, in the parentheses following the output period “R”, the colors R (red) and G displayed by the driven pixels are shown.
(Green), B (blue) and subscripts indicating the numbers of the row scanning electrodes to which the pixels belong are written. In the first horizontal scanning cycle of the first field, the signal H
₁ is at the “H” level, the signal H ₂ is at the “L” level, and the reset signal RS is at the “H” level during the horizontal retrace period of the horizontal scanning cycle. During this horizontal retrace period, the reset signal RS and the signal H
The output of the AND circuit 25 whose ₁ is connected to the input terminal becomes “H” level. Thereby, the analog switch 4 _A 1
And 4 _B l is turned on. Therefore, S / H-A and B
Performs a sampling operation, for example, a reset operation of a black level image signal. As a result, the hold voltage of the S / H-A and B hold capacitors 5 immediately before the horizontal effective display period becomes a black level voltage. Meanwhile, three primary color image signals Red, Gre, the shift matrix circuit 26 which receives the Blu X _R in the first horizontal period, X _G, X
Red, Gre, and Blu signals are output to each signal line of _B , respectively, and S / H-1 and B are each output during the horizontal effective display period.
d, Blu sampled. At this time, the sample and hold circuit with a small number 1 samples near the beginning of the horizontal effective display period, and the sample and hold circuit with a large number 1 samples near the end of the horizontal effective display period. The same applies to the operation during the horizontal effective display period after the second horizontal scanning cycle. In the first half of the subsequent second horizontal scanning period, the first row scanning electrodes
At the same time 10-1 is selected, the signal R ₁ commensurate with the pixels of the first row from the S / H-A is added to the column signal electrodes 9-l. In the latter half of the second horizontal scanning cycle, the second row scanning electrode 10-2 is used.
There simultaneously selected, signals B ₂ commensurate with the second row of pixels from the S / H-B is added to the column signal electrodes 9-l. At the same time, during the horizontal retrace period of the second horizontal scanning cycle, the reset signal RS
And has a signal H ₂ is "H" level, S / H-C and D sampling of the black level image signals, i.e., the reset operation is performed. As a result, the hold voltage immediately before the horizontal effective display period of all the S / H-C and D hold capacitors 5 is a black level voltage. On the other hand, the shift matrix circuit 26 in the second horizontal scanning period is X _R, X _G, respectively to the signal lines of X _B Gre, Blu, it outputs a Red signals during the horizontal effective display period S / H-C And D sample Gre and Blu, respectively. In the first half of the third horizontal scanning cycle, the third row scanning electrodes 10
-3 signals G ₃ commensurate with the pixels of the third row is added to the column signal electrodes 9-l simultaneously from S / H-C when selected. In the latter half, the fourth row scanning electrode 10-4 is selected and at the same time, S /
Signal R ₄ from H-D commensurate with the pixels of the fourth line is added to the column signal electrodes 9-l. Also after the third horizontal scanning period in which similarly to the first horizontal scanning period S / H-A and B and the reset operation in the horizontal retrace period, the shift matrix circuit 26 X _R, X _G, X _B
Since the signals of Blu, Red, and Gre are output to the respective signal lines, S / H-A and B sample Blu and Gre, respectively, during the horizontal effective display period. Hereinafter, the same operation is repeated, and when the number of pixels in the vertical direction is, for example, 480 pixels, the three primary color image signals are sampled during the 240 horizontal scanning periods, and all the pixels are sampled once until the 241st horizontal scanning period. Selective driving will be performed. Assuming that, for example, an interlaced NTSC image signal is handled as a television image signal, one field includes a 262.5 horizontal scanning cycle. Accordingly, the display based on the image signal in the 263rd horizontal scanning cycle is positioned higher than the display based on the image signal in the first horizontal scanning cycle, and the display based on the image signal in the 264th horizontal scanning cycle is performed based on the image signal in the first horizontal scanning cycle. Should be below the indication by. In consideration of this relationship, in the second field, only the pixels in the first row are driven by the image signal in the 263th horizontal scanning cycle, and the pixels in the second and third rows are driven by the image signal in the 264th horizontal scanning cycle. ing. Therefore, a signal obtained by the S / H-A sampling the image signal Gre during the 263rd horizontal scanning cycle is not applied to the pixel. This is indicated as R (X) in FIG. In this way, through the first and second fields, the 50th
All the pixels are selectively driven twice until four horizontal scanning periods. Therefore, by supplying a positive image signal to the first field and a negative pixel signal to the second field, for example, the driving voltage of the liquid crystal cell 12 is changed by AC driving at a two-field cycle, that is, a frame cycle (30 Hz). Will be done. As described above, in the embodiment of FIG. 5, the hold voltage of the hold capacitor 5 immediately before each sample-hold circuit starts sampling during the horizontal effective display period is always a black level voltage. Hold capacitance 5 independent of signal voltage sampled before horizontal scanning cycle
Of the hold voltage can be reduced.
The same effect can be obtained by replacing the circuit in the broken line frame indicated by the symbol SR in FIG. 5 with the circuit shown in FIG. The reset signal shown in FIG. 6 RS is "H" level over the horizontal retrace period, but the period of the immediately preceding horizontal effective display period, the television picture signal V _I is in the black level " A narrower reset signal such as H level may be used. This signal is denoted by RS 'in FIG. [Effects of the Invention] As described above, according to the present invention, each sample and hold circuit always samples the same constant voltage, for example, a black level voltage before sampling a television image signal during the horizontal effective display period. Therefore, sampling can be performed without being affected by the signal voltage of the previously sampled television image signal, and variation in the signal voltage held by the sample and hold circuit can be reduced. When using a signal whose polarity is inverted every horizontal scanning period as an alternating television image signal applied to the liquid crystal and causing each sample and hold circuit to perform sampling every horizontal scanning period, immediately before starting sampling of the television image signal If the voltage held by each sample-and-hold circuit is always set to a voltage approximately at the center of the amplitude of the AC-converted TV image signal, the maximum change voltage of the hold capacity at the time of sampling can be reduced to almost half of the amplitude of the AC-converted TV image signal. Therefore, the writing time for keeping the hold voltage within a predetermined error with respect to the image signal applied voltage can be substantially reduced by half. Alternatively, since the impedance of the analog switch used in the sample-and-hold circuit can be increased for the same required write time, the area occupied by the analog switch can be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a drive circuit for an active matrix type image display device according to the present invention, FIG. 2 is an operation waveform diagram of the embodiment of FIG. 1, and FIG. Is a circuit diagram showing a horizontal scanning shift register according to an embodiment of the present invention, FIG. 4 is an operation waveform diagram of the circuit example of FIG. 3, and FIG. 5 is a driving circuit of an active matrix type image display device according to the present invention. FIG. 6 is a configuration diagram showing another embodiment, and FIG. 6 is an operation waveform diagram of the embodiment of FIG. 1 ... horizontal scan shift register 2 ... OR circuit 3 ... level shifter 4 ... analog switch, 5, 7 ... hold capacity 6 ... output control buffer amplifier 8 ... vertical scan shift register 9 ... Column signal electrode, 10 Row scanning electrode 13 Liquid crystal panel 24 RS flip-flop

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Ko Nobuaki               292 Yoshida-cho, Totsuka-ku, Yokohama-shi Co., Ltd.               Hitachi, Ltd. (72) Inventor Minoru Wada               3681 Hayano Mobara-shi Hitachi Device En               Within Zineering Co., Ltd.                (56) References JP-A-61-117599 (JP, A)                 JP-A-49-87230 (JP, A)                 JP-A-59-153388 (JP, A)                 JP-A-61-116393 (JP, A)                 Actual opening sho 59-134972 (JP, U)

Claims (1)

(57) [Claims] In a matrix image display device provided with a plurality of pixels arranged in a matrix and corresponding to a plurality of pixels constituting a screen, and having a sample and hold unit for sampling and holding an image signal whose polarity is inverted in synchronization with a horizontal scanning cycle, The sample-and-hold means, after sampling a black level signal in a horizontal retrace period of the image signal immediately after the polarity is inverted, and then sampling an image signal in a horizontal effective display period immediately after the horizontal retrace period. A matrix image display device comprising: 2. Sample-and-hold means for sampling and holding an image signal whose polarity is inverted in synchronization with a horizontal scanning period, provided in correspondence with a plurality of pixels arranged in a matrix and constituting a screen; A shift register that outputs a pulse signal for performing an operation, wherein the sample-and-hold means samples and resets a signal voltage having the same polarity as the image signal to be sampled within a horizontal retrace period of the image signal. Wherein the shift register is configured to output the pulse signal during a horizontal effective display period after the sample-and-hold unit has performed the reset operation. Image display device.