JPH0482387A - Scanning line number conversion image display device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an image display device using a matrix display panel such as a liquid crystal panel, and particularly relates to an image display device that uses a matrix display panel such as a liquid crystal panel, and particularly relates to an image display device that displays a video signal having a first number of scanning lines. If you have a matrix display panel that has as many pixels as possible, and you want to display a video signal on the matrix display panel that has a second number of scanning lines that is greater than the number of first scanning lines, The present invention relates to a pixel display device that converts the number of scanning lines and enables display by thinning out the number of scanning lines from among the number of scanning lines.

[Conventional technology]

There are various types of color televisions, including NTSC, P
Three systems, the AL system and the SECAM system, are the mainstream in the world. In addition to these, high-definition high-definition systems are being experimented with, and color television systems are becoming increasingly diverse.

Generally, in order to reproduce and display a TV signal as a normal image on a matrix display panel, the TV signal is processed according to each system, and at the same time, a matrix display panel with the number of pixels corresponding to the number of scanning lines of each system is used. There is a need.

That is, a matrix display panel in which the number of pixels matches the number of scanning lines of a certain system cannot normally be used as is for pixel display of another system with a different number of scanning lines.

On the other hand, in Japanese Unexamined Patent Application Publication No. 169884/1984, the horizontal scanning line is controlled by controlling the clock of the vertical shift register of the vertical scanning circuit using an NTSC matrix panel having 220 pixels in the vertical direction. This patent discloses a technology that enables PAL television image display with a horizontal scanning line count of 275 by thinning out one in five lines. Furthermore, in order to provide a natural PAL image, in a known example, the position of one horizontal scanning line to be thinned out is changed between the first field and the second field.

[Problem to be solved by the invention]

When the thinning positions match in the first field and the second field, there is a problem that the horizontal line corresponding to the thinning position disappears from the displayed image.

FIG. 14 is an explanatory diagram showing the relationship between the panel line number of the liquid crystal panel 18 and the write signal scanning line number in one field before and after thinning out. That is,
What was shown in Figure 14(a) before thinning,
As shown in FIG. 14(b), when writing scanning line number 6 is thinned out in the first field and the second field, the - screen (-frame) consists of the first field and the second field, so Write scan line number 6 is no longer displayed on the screen at all; for example, the horizontal line that was on this line disappears. For this reason, in the known example, an operation is performed to change the thinning position between the first field and the second field.

However, in this case, there are rows in which the positions of the displayed scanning lines differ between the first field and the second field, which creates a problem in which the horizontal lines appear thick.

FIG. 15 is a diagram for explaining this, and shows the relationship between the panel line number of the liquid crystal panel 18 and the writing scanning line number when the position of the thinning scanning line is changed between the first field and the second field. FIG. That is, in the first field of FIG. 15(a), the write signal scanning line number 6 is thinned out, and in the panel line numbers 3 and 4.5, the write signal scanning line numbers are 3 and 4.5.

On the other hand, in the second field of FIG. 15(b), write signal scanning line number 3 is thinned out, so in panel line numbers 3 and 4.5, write signal scanning line numbers 4 and 5.6 are thinned out.
For example, if there is a horizontal line signal only in write signal scanning line number 4, the actual display will be over two lines depending on that of the first field and that of the second field.
It looks thick.

SUMMARY OF THE INVENTION An object of the present invention is to provide a scanning line number conversion image display device that can obtain a relatively natural image by thinning out such image discontinuity so that it is not noticeable.

[Means to solve the problem]

The above purpose is not to completely thin out the signals of - one scanning line, but to thin out the signals of two vertically adjacent scanning lines by half each, and the remaining one constitutes one scanning line. This is achieved by thinning out one scanning line.

FIG. 20 is a conceptual diagram showing the basic configuration of means for solving the problem.

In the same figure, the upper sample hold circuit SH (U)
Now, assuming that the -horizontal scanning line consists of eight pixel data numbers 1 to 8, the first pixel data among them ■
, the third pixel data ■, the third pixel data ■, and the seventh pixel data ■ can be sampled and held.

The lower sample hold circuit SH (L) receives the second pixel data (■), the fourth pixel data (■), and the sixth pixel data (■) among the eight pixel data of the horizontal scanning line.
, pixel data (■) at the eighth exit can be sampled and held.

One scanning electrode (A) from the vertical scanning circuit S and a signal electrode from the upper sample hold circuit 5H (U).
Display elements indicated by ○ are arranged at each intersection of ■, ■, ■ and the signal electrode from the lower sample-and-hold circuit SH (L) ■, ■, ■, ■, and large pixels surrounded by broken lines. A one-line matrix display device M is formed.

The upper horizontal shift register 5R (U) is for taking in image data given via the signal path K pixel by pixel into the sample and hold circuit 5H (U) by being supplied with a clock. The horizontal shift register 5R(L) is provided with a clock to take in image data given via the signal path K pixel by pixel into the sample-and-hold circuit 5H(L).

[Effect]

The circuit operation will be explained with reference to FIG. First, the operation when scanning lines are not thinned out will be described.

When eight pixel data belonging to one horizontal scanning line are supplied from the signal path K, among the eight pixel data belonging to the same horizontal scanning line, pixels ■, ■.

■, ■ are taken into the sample hold circuit 5H (U),
Sample and hold circuit SH (L) for pixels ■, ■, ■, ■
Incorporate into. Then, by driving one scanning electrode (a) from the vertical scanning circuit vS, one horizontal scanning signal input from the signal path K is displayed on one line of matrix display device M consisting of large pixels surrounded by a broken line. Eight pixel data belonging to a line can be displayed.

Next, an explanation will be given of the operation when one scanning line is thinned out from two scanning lines and displayed.

When eight pixel data belonging to the first horizontal scanning line are supplied from the signal path K, pixel ■ among the eight pixel data belonging to the horizontal scanning line.

■, ■, ■ are taken into the sample hold circuit 5H (U), and the other pixels are discarded. Next, eight pixel data belonging to the second horizontal scanning line are supplied from the signal path K, and of the eight pixel data belonging to the horizontal scanning line, pixels ■, ■, ■, ■ are sampled and held. Circuit SH(L
) and discard other pixels. Under such conditions, one scanning electrode (a) from the vertical scanning circuit ■S
, pixels ■, ■, among the eight pixel data belonging to the first horizontal scanning line inputted from the signal path K are displayed on the one-line matrix display device M consisting of large pixels surrounded by the broken line. The pixels ■, ■, ■, and ■ among the eight pixel data belonging to the second horizontal scanning line can be displayed. In other words, the two horizontal scanning lines, the first and second, are thinned out to one and displayed.

In this way, it is almost the same as taking the average of two vertically adjacent horizontal scanning lines, so one horizontal scanning line will not be completely missing, and discontinuities in the image will be noticeable. It's gone. Further, since the horizontal scanning lines can be displayed at the same position in the first field and the second field, it is possible to display a natural thinned-out image.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an embodiment of a scanning line number conversion image display device according to the present invention. Figure 1 shows a PAL image (hereinafter simply PAL image) with 287 effective display scanning lines in one field.
, also referred to as an L image), by thinning out every six lines to reproduce the PAL image on a liquid crystal panel having 240 vertical pixels.

The block diagram shown in FIG. 1 includes a signal circuit 7, horizontal scanning circuits 14-1 and 14-2, a vertical scanning circuit (vertical shift register) 15, and a liquid crystal panel 18.

Further, the signal circuit 7 includes a video signal (video) input terminal 1, a synchronization separation circuit 2, a control circuit 3, a video signal processing circuit 4, a polarity switching circuit 5, a thinning circuit 6, and a horizontal scanning circuit 14- 1 and 14-2 are arranged above and below the liquid crystal panel 18, and are input terminals 11-1 for horizontal shift registers 8-1, 8-2 and their shift clocks, data signals, etc.
, 11-2, sample hold circuit 9-1.9-2 and its three primary color RGB video signal input terminal 13-1.13-
2. n buffer amplifiers 10-1 and 10-2 for outputting sample and hold signals and an OE terminal 12 for controlling their output
-1.12=2.

The liquid crystal panels 18 are horizontally arranged vertically with each other.
n signal electrodes (n upper side, n lower side)】6-1.16
-2, one vertical scanning electrode 17, drain,
It is composed of m x 2 n thin film pixel transistors (TPT) 19 whose gates are selected, and a liquid crystal pixel 2o connected to the source of each pixel transistor.

The operation of the circuit shown in FIG. 1 is as follows.

A synchronization separation circuit 2 separates horizontal and vertical synchronization signals from a PAL video signal input to an input terminal 1. Based on the horizontal and vertical synchronizing signals, control signals necessary for driving the horizontal scanning circuits 14-1 and 14-2, the vertical scanning circuit 15, and the polarity switching circuit 5 are formed in the control circuit 3.

On the other hand, in the video signal processing circuit 4, the input PA
The L video signal is processed to form RGB primary color signals. Note that in the case of a monochrome video signal instead of a color video signal, the video signal is a luminance signal and is similar, so the following description of this embodiment will be made assuming color display.

After the polarity of the video signal is switched at regular intervals in the polarity switching circuit 5, it is applied to sample and hold input terminals 13-1 and 13-2 of the horizontal scanning circuit 14-1, 14-2. In the horizontal scanning circuit 14-1.14-2, the input terminal 11-
The horizontal shift register 8-1゜8-2 operates based on the signal inputted to 1.11-2 via the thinning circuit 6, and samples are processed according to the output of the shift register 8-1.8-2. Hold circuit 9~1゜9-2 is terminal 13-1.13-
At the same time, the data is held for a predetermined period of time.

After the sampling of the image signal of one line (-horizontal scanning line) is completed, the output of the sample hold circuit 9-1, 9-2 becomes the input of the buffer amplifiers 10-1, 10-2, and the buffer amplifiers 10-1, The output of 10-2 is OEl, ○ applied to its control terminals 12-1 and ll-2.
The signal is applied to the signal electrodes 16-1 and 16-2 of the liquid crystal panel 18 in response to E2 (Output-Enable signal).

On the other hand, a vertical scanning circuit 15 composed of a shift register
Now, from the control circuit 3 via the thinning circuit 6,
For example, m scanning electrodes 17 of the liquid crystal panel 18 are sequentially selectively driven based on a signal obtained by thinning out the clock. i
When the scan electrode 17-1 in the th row is driven, 2n transistors (19-i, 1) to (19-i) in the horizontal direction whose gates are connected to the electrode are activated.

2n) turns ON simultaneously. At this time, buffer amplifier 1
In synchronization with the OEI and ○E2 signals applied to the control terminals 12-1 and 12-2 of 0-1.10-2, the sample-and-hold image signal is output to the sample-and-hold circuit 9-1.9-2. The image transistor (1
A sampling image signal is written to the liquid crystal pixels (20-i, 1) to (20-i, 2n) via 9-i, 1) to (19-i, 2n). That is, image information is written on the i-th line of the liquid crystal panel 18.

Hereinafter, the thinning circuit 6 in FIG. 1, which is an embodiment of the present invention, will be described.
The operation will be explained in detail.

FIG. 2 shows a waveform diagram of main signals necessary for the circuit operation of FIG. 1. The signals shown in FIG. CPH (equivalent to clock)
I, horizontal shift register 8- applied to terminal 11-2
2 start pulse 5TH2 and its shift clock C
PH2, start pulse STV of the vertical scanning circuit 15 and its shift clock CP■, control signals OEI and OEI of the buffer amplifiers 10-1 and 10-2 applied to the terminal 12;
It is E2.

Vertical scanning starts based on the rise of the vertical shift clock CPv at the time of inputting the start pulse STV of the shift register in the vertical scanning circuit 15. In Figure 2,
The pulses of each related signal are given the same number. That is, the signal related to the first horizontal scanning period is numbered 1, the signal related to the second horizontal scanning period is numbered 2, and so on.

That is, at the rising edge of pulse 1 of CPv, a scanning pulse is output from the first stage of the vertical shift register 15, and the first scanning electrode 17-1 of the liquid crystal panel 18 is driven.

On the other hand, 5TH1 and 5T synchronize with Hsync pulse 1 approximately one horizontal period before CPV pulse 1.
The image signal R is held in the sample hold 9 (9-1, 9-2) by the H2 pulse. This sampling data is outputted from the buffer amplifiers 10-1 and 10-2 by control signals OE1 and OE2 that rise approximately -horizontal scanning period after Hsync 1, and is output from the liquid crystal panel 18.
is written on the first line. The waveform of the signal electrode 16-1.1 is the waveform 16-1.1 of FIG. 2, and the waveform of the signal electrode 16-2
．． The waveform of l becomes waveform 16-2.1 in FIG.

In the thinning circuit 6 shown in FIG. 1, for example, as shown in FIG. 2, 5THI is cpv after pulse 6.

In the OE, pulses 5 and subsequent pulses are successively thinned out at intervals of one in six pulses (the thinned out pulses are indicated by broken lines).

At this time, since pulse 6 of 5THI is interrupted, image signal R 6 is not sampled in the sample-and-hold circuit 9-1, and data of image signal R 5 remains held.

On the other hand, in the sample hold circuit 9-2, the 5TH
6 of the image signal R is sampled by the pulse 6 of 2. Further, the vertical shift register 15 does not operate at the time corresponding to pulse 5 of CPV and remains stopped in the state of pulse 4 of CPV. The signal waveforms applied to the scanning electrode 17 are 17-1°1'l-2, 17-3, 17- in FIG.
The sequential selection waveforms shown in 4 and 17-5 are obtained. That is, the state in which the fourth line of the liquid crystal panel 18 is selected is CPV5.
will continue for a period of

At this time, since the pulses 5 of the control signals ○El and OE2 are also stopped at the same time, there is no change in the contents of the pixels of the fourth line, and 4 of the image signal R continues.

After the fifth line is selected by the CPV pulse, the signal electrode 16-
5 data of the image signal R is output to the signal electrode 16.
-2, data of image signal R 6 is output. Therefore,
As the pixels of the fifth line of the liquid crystal panel 18, signals No. 5 and No. 6 of the image signal R are alternately written and displayed simultaneously.

FIG. 3 shows the relationship between the scanning lines of the write signal displayed on the liquid crystal panel 18 by the thinning circuit 6 and the line numbers on the liquid crystal panel 18.

FIG. 3(a) shows the relationship during the odd field display period. The liquid crystal panel 18 has 240 pixels in the vertical direction, and has 240 pixels in the vertical direction.
40 scan lines can be written.

The scanning lines that can be written on the liquid crystal panel 18 are numbered and are written as panel line numbers on the left side of FIG. 3(a). On the other hand, the scanning line number of the image signal actually written is written on the liquid crystal panel 18 in FIG. 3(a).

According to the explanation of the waveform diagram in FIG.
, OE2, the image signals of two scanning lines are displayed alternately in the horizontal direction on one panel line as shown in panel line number 5 in FIG. 3(a). If you do this, the averaged signal of two adjacent scanning lines will be displayed, and image signals will be written in five out of every six lines.

As a result, as shown in FIG. 3(a), an image signal in which one out of every six scanning lines is thinned out is written on the liquid crystal panel 18, so that the liquid crystal panel 18 is composed of 240 lines.
8, an image of an odd field, which is originally composed of 287 scanning lines from the -wood grain, is displayed in a vertically reduced state.

Similarly, even in the even field shown in FIG. 3(b), the screen of the even field, which originally consists of 287 scanning lines (313th, 599th, etc.), is reduced vertically on the liquid crystal panel 18. Is displayed.

FIG. 4 shows a thinning relationship that aims at a more natural display than the thinning relationship shown in FIG. In FIG. 3, the order of the two write signal scanning line numbers written to one panel line of the liquid crystal panel 18 is such that the smallest number is on the left side for both the odd and even fields. That is, −
In a frame, image signals at the same position are thinned out. On the other hand, in FIG. 4, the above order is changed between odd and even fields so that the thinning becomes uniform.

In this case, instead of the start pulse 5THI in Figure 2,
It is necessary to thin out 5TH2. That is, when one of the start pulses 5THI to 5TH2 is thinned out, the other start pulse is not thinned out.

Therefore, according to the invention shown in FIG. 4, the discontinuity in the image becomes less noticeable, and the liquid crystal panel 18 with an aspect ratio of 4:3 has a
PAL images can be displayed more naturally with the same aspect ratio of 4:3.

FIG. 5 shows a specific circuit configuration example of the thinning circuit 6 in FIG. 1. The circuit shown in FIG. 5 can be roughly divided into two blocks. One is the thinning pulse generation circuit 21 and the other is the gate circuit 37.

The thinning pulse generation circuit 21 includes a counter 25 and timing adjustment circuits 26, 27, and 28. counter 2
5 is input to the terminal 24 with reference to STV (start pulse ■) input to the terminal 23, for example, H
sync (horizontal synchronization signal) is counted every six.

That is, the counter 25 generates a pulse every six Hsyncs.

Based on this pulse, the timing adjustment circuit 26 generates a negative pulse that covers pulse 5 (dashed line) of cPV in FIG. 2, and the timing adjustment circuit 27 generates a pulse 5 of OE.
(dashed line), and the timing adjustment circuit 28 generates a positive pulse that covers pulse 6 of 5TH1 (dashed line).

The timing adjustment circuit includes a delay circuit 6 as shown in FIG.
1 and a monostable multivibrator 62, the gate circuit delays a pulse input to a terminal 59 for a certain period of time in a delay circuit 61, forms a pulse of a certain width in the monostable multivibrator 62, and outputs it from a terminal 6o. 37 mainly consists of four AND circuits and two NA
It consists of an NDAND inverter circuit. AND
33 gates the cPV input to the terminal 3o with a thinning pulse from the timing adjustment circuit 26. Furthermore, by setting the thinning pulses from the timing adjustment circuit 26 to have negative polarity, the cPV pulses input to the terminal 3o are thinned out at a rate of one in six, and are output from the terminal 38.

Similarly, in AND34, OE input to terminal 31
The pulses are also thinned out at a ratio of one in six in the AND 34, and are output from terminals 63 and 64 as OEI and OE2. In the NAND 57, based on the field discrimination signal FD, in an odd field or an even field,
The positive polarity pulse of the timing adjustment circuit 28 is outputted with negative polarity.

According to this pulse, the AND 35 thins out the STH pulses input to the terminal 32 at a ratio of one in six pulses and outputs them to the terminal 40 as 5 THI. Similarly, NAND5
8, the positive polarity pulse of the timing adjustment circuit 28 is output with negative polarity in a field different from the NAND 57 based on the output of the inverter 29 to which the field discrimination signal FD is input.

According to this pulse, the AND 36 thins out the STH pulses input to the terminal 32 at a ratio of one out of every six pulses and outputs it to the terminal 41 as 5TH2. Note that the field discrimination signal FD is formed from a vertical synchronizing signal and has a period twice that of the vertical synchronizing signal.

In addition, the gate circuit 37 is connected to the ST input to the terminal 23.
V, CPH1 input to the terminal 67, and CPH2 input to the terminal 68 as they are, to the terminal 66 (STV).

Output to terminal 69 (CPHI) and terminal 70 (CPH2).

In this way, if the circuit shown in FIG. 5 is used for the thinning circuit 6 shown in FIG. 1, the thinning display shown in FIG. 4 can be achieved. Note that in order to perform the thinning display shown in FIG. 3, the inverter 29 in FIG.
This becomes possible by setting the input line to which 9 was connected to the "H" state. At this time, only the 5THI pulse is thinned out, and the 5TH2 pulse is not thinned out.

A second embodiment of the present invention is shown in No. 7 FXJ. Figure 7 shows
The wiring of the gate circuit 37 in FIG. 5 is changed, and the pulses to be thinned out are changed from STH to CPHI and CPH2.

In the gate circuit 437 of FIG. 7, CPHI and CPH2 applied to the terminals 67 and 68 are AND35°
36 is entered. As a result, for example, S
At the timing when the TH pulse 6 is thinned out, the CPHI pulse is thinned out (during the period when the STH pulse 6 is "H"). This is shown in the waveform diagram of FIG.

Note that 5THI and 5TH2 do not need to be thinned out in this case, and the STH input to the terminal 32 is directly sent to the terminal 40.
Just output them as 5THI and 5TH2 to terminal 4■.

In this way, the shift clocks CPHI and CPH2 of the horizontal shift register 8-1.82 are set to "H" at least 5THI (or 5TH2) once every six horizontal scanning periods.
By thinning out the cells for a period of , the effect completely equivalent to that of the first embodiment can be obtained.

A third embodiment of the present invention is shown in FIG. 9, and a waveform diagram of the main signals is shown in FIG. 10. FIG. 9 shows a portion of the thinning circuit 6 shown in FIG.

In the first example, 5THI and 5TH2 were thinned out, and in the second example, CPHI and CPH2 were thinned out. In the third embodiment, OEI and OE2 are thinned out.

The thinning pulse generation circuit 521 in FIG. 9 includes a counter 6 and timing adjustment circuits 26, 527, 528, and 72. Among these, what is different from FIG. 5 is the timing adjustment circuits 527, 528, and 72. The timing adjustment circuit 527 generates a negative polarity pulse (dashed line) that covers pulse 5 of OEI (or 0E2), and the timing adjustment circuit 528 generates a negative polarity pulse (dashed line) that covers pulse 6 of 0E2 (or 0EI). Generates a pulse. Further, the timing adjustment circuit 72 adjusts the pulse half of the scan electrode 17-4 (
A pulse of negative polarity covering the broken line portion) is generated and outputted from the terminal 73 as a signal name M. The signal M is a signal that controls the output of the vertical scanning circuit 15, and when M has negative polarity, the output of the vertical scanning circuit 15 is prohibited and no gate line is selected.

Gate circuit 537 consists of AND33, 35, 36 and multiplexer 74,75. Among these, the role of AND33 is exactly the same as that in FIG. The output of the timing adjustment circuit 527 or 528 is selected by the multiplexer 74 and inputted to the AND 35 based on the FD signal applied to the terminal 22.

As a result, for example, when the signal of the timing adjustment circuit 527 is selected, pulse 5 of the ○E pulses applied to the terminal 31 is thinned out by the AND 35, and is output from the terminal 63 as the signal of OE1.

Note that multiplexers 74 and 75 are interlocked and select the outputs of timing adjustment circuits 527 and 528.

The selection operation is determined such that, for example, when the output of the multiplexer 74 is the timing adjustment circuit 527, the output of the multiplexer 5 is the timing adjustment circuit 528 (or vice versa). On the other hand, the output of the timing adjustment circuit 128 (or 127) is input to the AND36. At this time, among the OE pulses, pulse 6 is AND3
6 and output from the terminal 64 as OE2.

Therefore, the signals of the signal electrodes 161.1 and 16-2.1 become as shown at 16-1.1 and 16-2.1 in FIG. If we pay attention to the waveform 17-4 of the scanning electrode 17-4, for example, compared to the waveform 17-3, the pulse width is expanded by the portion indicated by the broken line.

During the period indicated by the broken line, the waveform 16-1.1 is the content of the video signal R4, and the waveform 16-2.1 is the content of the video signal R5. The fourth and fifth wood will be displayed mixed together.

Therefore, the broken line portion 17-4 is controlled by the M signal. That is, 17-4 appears as a solid line, and the fourth and fifth horizontal scanning lines are not displayed in the fourth row of the liquid crystal panel 18 in a mixed manner.

By thinning out OEI and OR3 in the manner described above, effects completely equivalent to those of the first embodiment can be obtained.

A fourth embodiment of the invention is shown in FIG. A feature of FIG. 11 is that in every row of the liquid crystal panel 218, there are two gate lines for one row of pixels in the horizontal direction. Here, the pixel 55 in FIG. 11 may be considered to be equivalent to the combination of the pixel transistor 19 and the liquid crystal pixel 20 in FIG.

For example, the two gate lines assigned to one row are 55~
Gate lines 217 to 5 and 217-6 are arranged for five rows of pixels. That is, 5 of the pixels in one row
5-5.1.55-5.3.55-5. (2n-1)
is connected to the gate line 217-5, and the remaining pixels 55-
5.2.55-5.4.55-5. (2n) is connected to the gate line 217-6. In the vertical scanning circuit 215, a shift register is formed by a flip-flop 53 of the same faith as the gate line, and a gate 217 is driven by a buffer amplifier 52.

The gate lines 217-5 and 217-6 are determined by the switch 56 to be selected simultaneously or sequentially. This means that the flip-flops 53-4 and 53-5 are connected to the data 54 of 53-4.
-4 is received at the same time, but the difference is whether 53-4 and 53-5 are received sequentially.

Therefore, when the gate lines 217-5 and 217-6 are selected at the same time, a television signal system display having the same number of horizontal scanning lines as the horizontal pixels of the liquid crystal panel 218 can be performed.

Furthermore, if the gate lines 217-5 and 217-6 are selected sequentially, the same effect as in the first embodiment can be obtained.

In the fourth embodiment, thinned-out display is possible simply by switching the switch 56.

A fifth embodiment of the present invention is shown in FIG. The feature of the fifth embodiment is the liquid crystal panel 318. In the fourth embodiment, two gate lines were arranged in some rows, but in the fifth embodiment, two gate lines were added across all rows. The arrangement of the two gate lines is as described above, so it will not be described here.

Further, in the vertical direction, - signal lines are arranged for two adjacent pixels. For example, pixels 55-1.1 and 55-1
．． A common signal line is arranged in the second column.

As a result, even if either pixel 55-1.1 or 55-1.2 is damaged, as long as the other one is intact, display in the first horizontal row and the first vertical row can be performed.

The differences from FIG. 1 are the structure of the liquid crystal panel 318, the arrangement of the horizontal scanning circuit 14, the arrangement of the vertical scanning circuit 15, and the thinning circuit. One horizontal scanning circuit 14 was arranged above the liquid crystal panel 318, and one vertical scanning circuit 15 was arranged on both left and right sides of the liquid crystal panel 318.

The operation shown in FIG. 12 will be explained based on the waveform diagram shown in FIG. 13. Horizontal synchronization signal Hsync, image signal R1 horizontal shift register start pulse STH and its shift clock CPH, vertical shift register start pulse STV
, the output control OE signal has already been described, so it will not be explained here.

CPVI is the shift clock of the vertical shift register in the vertical scanning circuit 15-1, and CPV2 is the shift clock of the vertical shift register in the vertical scanning circuit 15-1.
This is the shift clock of the vertical shift register in 5-2. Further, Ml is a signal that controls the output of the vertical scanning circuit 15-1, and when Ml has negative polarity, the vertical scanning circuit 15-1
-1 output is inhibited and no gate line is selected.

Similarly, M2 is an output control signal of the vertical scanning circuit 15-2.

In order to obtain the same effect as in the first embodiment, here, CP
Thin out VI and CPV2. For example, by thinning out pulse 6 of CPVI in FIG. 13 and pulse 5 of CPV2, the gate line 17-2.4.17-2.5 has a waveform including a broken line in FIG. Furthermore, M1 signal grin, 17-1.
The broken line portion of 5 is controlled by the M2 signal, and the broken line portion of 1'7-2.4 is controlled by the M2 signal. That is, 17-2, 4.17-1
．． 5 looks like a solid line.

At this time, first, the fourth row of the liquid crystal panel 318 is connected to the gate line 1.
7-1, 5, and 17-2.4 are simultaneously selected, and signal 4 on signal line 6 is written. Next, gate line signal 17-
1.5, the odd-numbered pixel in the fifth row (55-5, 1,
55-5, 3...) is selected, the signal 5 of the signal line 16 is written, and the gate line signal 17-2.5 is also written.
The even numbered pixels of the fifth row (55-5, 2, 55-
5, 4, . . . ), the signal 6 of the signal line 16 is written. Therefore, the effects of the present invention can be obtained.

A sixth embodiment of the present invention is shown in FIG. This embodiment, as detailed in Japanese Patent Application Laid-Open No. 63-26084, samples a video signal of -horizontal scanning period, and in the first half and second half of one subsequent horizontal scanning period, pixels of adjacent parts are sampled. This is an example in which the present invention is applied to double-speed line sequential scanning in which the 3D images are driven separately.

16E has basically the same circuit configuration as that in FIG. The difference is that only the vertical scanning circuit 315 is controlled by the signal from the thinning circuit 306, and the horizontal scanning circuit 214 is controlled by the signal from the thinning circuit 306.
is a point where no special control by thinning is performed.

A detailed block diagram of the thinning circuit 306 is shown in FIG.

The basic configuration is also the same as that in FIG. 5, and the timing adjustment circuits 126 and 127 are as shown in FIG. Therefore, detailed explanation of the circuit operation will be omitted.

FIG. 17 is a diagram for explaining FIG. 16, and shows the relationship between panel line numbers and write signal scanning line numbers in the liquid crystal panel 418.

FIG. 19 is a diagram of main signal waveforms in FIGS. 16 and 18. In double-speed linear sequential scanning, the first field is usually the second field, i.e.
If no thinning is performed, as shown in Figure 17(a),
The same scanning line signal is written to adjacent sections. For example, write signal scanning line number 2 to panel line number 3°4.
signal is written.

Then, in the other field, the combination of panel line numbers is shifted, and the same scanning line signals are written in adjacent parts. For example, panel line number 2,
3, the signal of the write scanning line signal 2 is written.

When the thinning operation of the present invention is performed in this double-speed line sequential scanning, the result is as shown in FIG. 17(b). That is, the signals of write signal scanning line numbers 5 and 6 written in panel line numbers 10 and 11 shown in FIG. Write signal scanning line numbers 5 and 6 are written in parts 9 and 10. Thereby, in double-speed line sequential scanning, it is possible to take the average of two adjacent horizontal scanning lines.

The thinning operation of the sixth embodiment will be explained based on the main signal waveform diagram shown in FIG. In double-speed line sequential scanning, the first
The period of the shift clock CP■ of the vertical scanning circuit 315 in FIG. 6 is the minus part of the period of H8ync. Also, the control signal OE: has a period of - in the #JHsync portion.

Therefore, for example, the signal line 317-3 is selected by the pulse 2-1 of CP■, and the image signal 21 of the signal line 217 is written to the pixel selected by the signal line 317-3 by the pulse 2-1 of OE. be included.

Similarly, the image signal 2-2 on the signal line 217 is written into the pixel selected on the signal line 317-4. That is, the signal of the write scanning line number 2 is written in the panel line numbers 3 and 4 of the liquid crystal panel 418 in FIG.

Attention is now paid to pulses 5-2 and 61 of CP2 in FIG. These pulses are decimated by a decimation circuit 306, as shown by the dashed line.

Therefore, the output of the signal line 317-9 has a combination of a solid line and a broken line. Furthermore, by controlling the output of the vertical scanning circuit with the M signal, the output of the signal line 317-10 is
Only solid lines are shown.

At this time, the pixel selected by the signal line 317-9 has OE
The image signal 5-1 of the signal line 217 is written by the pulse 5-1 of OE, and the image signal 6-1 of the signal line 217 is written to the pixel selected by the signal line 317-10 by the pulse 6-2 of OE.
2 image signals are written. That is, Fig. 17 (b
), image signal 5 is written to panel line number 9 of liquid crystal panel 418, and image signal 6 is written to panel line number 10.

〔Effect of the invention〕

According to the present invention, by thinning out one line on average from the signals of adjacent horizontal scanning period partial portions, the number of scanning lines can be thinned out without completely losing one of the portions,
There is an advantage that an image having a larger number of scanning lines can be displayed naturally on a display panel having a smaller number of display scanning lines with less discontinuity.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
3 and 4 are explanatory diagrams showing the relationship between the panel line number and the scanning line of the display image signal in connection with the present invention, and FIG. 6 is a block diagram showing an example of the configuration of the main parts in FIG. 5; FIG. 7 is a block diagram showing a second embodiment of the present invention; FIG. 7 is a signal waveform diagram of the main part in FIG. 7, FIG. 9 is a block diagram showing the third embodiment of the present invention, 10th row is a signal waveform diagram of the main part in FIG. 9, FIGS. 11 and 12 The figures are block diagrams showing the fourth and fifth embodiments of the present invention, respectively, and FIG. 13 is a block diagram showing the twelfth embodiment.
Signal waveform diagrams of the main parts in the figure, FIGS. 14 and 15 are explanatory diagrams showing the relationship between panel line numbers and scanning lines of display image signals, and FIGS. The figure is a block diagram showing a sixth embodiment of the present invention.
FIG. 7 is an explanatory diagram showing the relationship between the panel line number and the scanning line of the display image signal in connection with the embodiment of the present invention, No. 18
The figure is a block diagram showing an example of the configuration of the main parts in Fig. 19, the signal waveform diagram of the main parts in Fig. 16, and Fig. 20.
The figure is an explanatory diagram showing the basic configuration of means for solving the problems of the present invention. 1... Video input terminal 3... Control circuit 5... Polarity switching circuit 14... Horizontal scanning circuit 18... Liquid crystal panel 61... Delay circuit 62... - Monostable multivibrator 2...・Synchronization separation circuit 4...Video signal processing circuit 6...Thinning circuit 15...Vertical scanning circuit 43, 56...Switch 17=5 Tremor? Diagram 4 Diagram 5 Diagram 〒6 Diagram 7 Diagram 艷■ Diagram 〒6 Diagram Yu 10 Diagram PV lZj4'5L-Door Rou Nikko 11-1.6 Child 1 Diagram ff 113 Senbon 12 Diagram Sanskrit 14 Diagram 15 Kasumi 〒I''7Fig.

Claims (1)

[Claims] 1. A matrix display panel having a number of pixels sufficient to display a video signal having a first number of scanning lines, and a second scanning panel having a number of pixels greater than the first number of scanning lines. When a video signal having a number of lines is to be displayed on the matrix display panel, the number of scanning lines is reduced by thinning out the number of scanning lines from the second number of scanning lines. In the apparatus, the matrix display panel includes a plurality of scanning electrodes extending in one direction, a plurality of signal electrodes extending in a direction crossing the one direction, and display elements arranged and connected in a matrix at intersections thereof; Divide the signal electrodes into multiple groups,
a horizontal scanning circuit with a sample and hold circuit connected to each group separately; a vertical scanning circuit connected to the plurality of scanning electrodes; and when displaying a video signal having the first number of scanning lines. teeth,
Supplying a drive signal for driving the vertical scanning circuit once after capturing and holding image information belonging to the same scanning line to each sample hold circuit of the plurality of sets of horizontal scanning circuits, and increasing the number of the second scanning lines. When displaying a video signal having a plurality of horizontal scanning circuits, a drive signal is supplied to each sample hold circuit of the plurality of sets of horizontal scanning circuits to drive the vertical scanning circuit once after capturing and holding image information belonging to different scanning lines. 1. A scanning line number conversion image display device, comprising: a drive signal supply circuit that performs the following steps. 2. A matrix display panel having a number of pixels sufficient to display a video signal having a first number of scanning lines, and a video signal having a second number of scanning lines greater than the first number of scanning lines. When attempting to display on the matrix display panel, in a scanning line number conversion image display device that reduces and displays the number of scanning lines by thinning out the scanning lines from the second number of scanning lines, The matrix display panel includes a plurality of extending scan electrodes, a plurality of signal electrodes extending in a direction crossing the one direction, and display elements arranged and connected in a matrix at the intersections thereof, and a plurality of sets of the plurality of signal electrodes. Divided into
a horizontal scanning circuit with a sample and hold circuit connected to each group separately; a vertical scanning circuit connected to the plurality of scanning electrodes; and when displaying a video signal having the first number of scanning lines. teeth,
Image signals are simultaneously output from the plurality of sets of horizontal scanning circuits, a drive signal for driving the vertical scanning circuit once is supplied, and a second number of scanning lines is greater than the number of first scanning lines. a drive signal supply circuit that separately outputs image signals from the plurality of sets of horizontal scanning circuits and supplies a drive signal to drive the vertical scanning circuit once;
1. A scanning line number conversion image display device comprising: 3. A matrix display panel having a plurality of scanning electrodes extending in one direction and a plurality of signal electrodes extending in a direction crossing the one direction, and display elements arranged and connected at the intersection points;
In a matrix display device comprising a vertical scanning circuit connected to the scanning electrode and a horizontal scanning circuit connected to the signal electrode, all of the display elements in one direction and one row in the matrix display panel are of the same type. a row connected to a scanning electrode;
In one direction, rows in which each of the display elements constituting one row is alternately connected to two adjacent scanning electrodes are placed in the matrix display panel in a mixed manner, and the vertical scanning circuit connects the two adjacent scanning electrodes. 1. A scanning line number conversion image display device comprising a switch for selecting and driving the scanning electrodes simultaneously or sequentially. 4. A matrix display panel having a plurality of scanning electrodes extending in one direction and a plurality of signal electrodes extending in a direction crossing the one direction, and display elements arranged and connected at the intersection points;
In a matrix display device comprising a vertical scanning circuit connected to the scanning electrode and a horizontal scanning circuit connected to the signal electrode, each of the plurality of scanning electrodes has a first scanning electrode and a second scanning electrode. comprising a plurality of pairs of scan electrodes consisting of pairs of electrodes, each of the display elements constituting one row in one direction in the matrix display panel being alternately connected to the scan electrodes of the adjacent pair; A simultaneous sequential selection waveform is applied to some of the pairs of scan electrodes connected to the display elements constituting one row from the vertical scan circuit, so that some of the scan electrodes connected to the display elements constituting one row are provided with simultaneous and sequential selection waveforms from the vertical scan circuit. The remaining one of the pair of scan electrodes connected to the pair of scan electrodes is sequentially provided with a selection waveform shifted by one horizontal scan period with respect to the pair of scan electrodes from the vertical scan circuit. 1. A scanning line number conversion image display device comprising a drive signal source for driving a vertical scanning circuit. 5. A matrix display panel having a plurality of scanning electrodes extending in one direction and a plurality of signal electrodes extending in a direction crossing the one direction, and display elements arranged and connected at the intersection points;
In a matrix display device comprising a vertical scanning circuit connected to the scanning electrode and a horizontal scanning circuit with a sample-hold circuit connected to the signal electrode, the scanning electrodes are sequentially shifted by 1/2 horizontal scanning period. A number of scanning lines characterized by comprising a drive signal source that drives with a selected waveform and a clock source that can thin out and output two consecutive shift clocks that drive the vertical scanning circuit. Conversion image display device. 6. A matrix display panel having a plurality of scanning electrodes extending in one direction and a plurality of signal electrodes extending in a direction crossing the one direction, and display elements arranged and connected at the intersection points;
In a matrix display device comprising a vertical scanning circuit connected to the scanning electrode and a horizontal scanning circuit connected to the signal electrode, display elements in one direction and one row in the matrix display panel are arranged in one horizontal line. The matrix is formed by mixing rows that display image signals belonging to a scanning period and rows that alternately display image signals belonging to two adjacent horizontal scanning periods in one direction and each of the display elements constituting one row. A scanning line number conversion image display device characterized by displaying on a display panel.