JPH0321176A - Scanning line number conversion image display device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Application of Industry) The present invention relates to an image display device using a matrix display panel such as a liquid crystal panel, and more specifically, The matrix display panel has a number of pixels sufficient to display a video signal having a number of scanning lines of 1, and displays a video signal having a second number of scanning lines greater than the first number of scanning lines. This invention relates to a scanning line number conversion image display device that is capable of reducing the number of scanning lines and displaying the image on a matrix display panel by thinning out the number of scanning lines from the second number of scanning lines. be.

(Prior technology) There are various color television systems, and the three systems, NTSC, PAL, and SECAM, are the mainstream in the world.In addition to these systems, a high-definition high-definition system is also being experimented with. As a result, color television systems are becoming more and more diverse.

Generally, in order to reproduce and display a TV signal as a normal image on the 71-risk display panel, the TV signal must be processed according to each method, and at the same time, a matrix display with the number of pixels corresponding to the number of scanning lines of each method described above must be performed. It is necessary to use a panel.

That is, a matrix display panel in which the number of pixels matches the number of scanning lines of a certain system cannot normally be used as is for image display of another system with a different number of scanning lines.

On the other hand, in Japanese Unexamined Patent Publication No. 169884/1984, the chronograph of the vertical shift 1 register of the multi-direction scanning and parallel scanning is controlled by using an NTSC system multi-channel having 220 pixels in the vertical direction. By controlling the horizontal scanning line to 5
This paper discloses a technology that makes it possible to display PAL television images with a number of horizontal scanning lines of 275 per field by thinning the image at a ratio of 100% to 100%. Furthermore, in order to provide a natural PAL image, the position of one horizontal scanning line to be thinned out is changed between the first field and the second field. There is.

[Problems to be Solved by the Invention] If the thinning positions match in the first field and the second field, there is a problem that the horizontal line corresponding to the thinning position disappears from the displayed image.

FIG. 13 is an explanatory diagram showing the relationship between the panel line number of the liquid crystal panel l8 and the write signal scanning line number in one field before and after thinning out. That is,
Before the thinning, it was as shown in Figure 13(a),
As shown in FIG. 13(b), if write scanning line number 6 is thinned out in the first and second fields, one screen (one frame) is divided from the first and second fields. , write scan line number 6 is no longer displayed on the screen at all; for example, the horizontal line on this line disappears. For this reason, in the known example, the thinning position is changed between the first field and the second field.

However, in this case, since there are rows in which the positions of the displayed scanning lines differ between the first field and the second field, a problem arises in which the horizontal lines appear thick.

FIG. 14 is a diagram for explaining this, and shows the relationship between the pie and line numbers of liquid crystal panel ■8 and the write scanning line numbers when the positions of thinning scanning lines are changed between the first and second fields. FIG. That is,
In the I-th field of FIG. 14(a), the write signal scanning line number 6 is in the interval 4), and the write signal scanning line number 3, /I.
5, the write signal scan line numbers are 3, 4.5.

On the other hand, in the second field of FIG. 14(b), write signal scanning line number 3 is thinned out, so in panel line number 3, 4, 5, write signal scanning line number 4, 5, .
For example, if there is a horizontal line signal only in write signal scanning line number 4, the actual display will span two lines and appear thick due to the first field and the second field.

SUMMARY OF THE INVENTION An object of the present invention is to provide a scanning line number conversion image display device that can obtain a relatively natural image by thinning out such image discontinuity so that it is not noticeable.

q 10 [Means for solving the problem] The above purpose is not to completely thin out the signal of one scanning line, but to thin out the signals of two vertically adjacent scanning lines by half each, and reduce the remaining signal. This can be achieved by configuring one scanning line with , resulting in thinning out one tree's worth of scanning lines.

FIG. 19 is a conceptual diagram showing the basic configuration of means for solving the problem.

In the figure, the upper sample and hold circuit SH (U
) is now assumed to have ■horizontal scanning lines from eight pixel data numbers 1 to 8, among which the first pixel data■, the third pixel data■, the fifth pixel data■, 7
The th pixel data ■ can be sampled and held.

The lower sample hold circuit SH (L) is 1
Among the eight pixel data of the horizontal scanning line, the second pixel data (2), the fourth pixel data (2), the sixth pixel data (2), and the eighth pixel data (2) can be sampled and held.

One scanning electrode (A) from the vertical scanning circuit VS and a signal electrode from the upper sample hold circuit SH (U).
Display elements indicated by ○ are arranged at each intersection with ■, ■, ■ and each intersection with signal electrodes ■, ■, ■, ■ from the lower sample-and-hold circuit SH (L), and are surrounded by broken lines. A one-line matrix display device M consisting of eight pixels is used.

The upper horizontal shift register SR (U) is supplied with a clock to sample and hold circuit SH (U) the image data given via the signal path K pixel by pixel.
The lower horizontal shift register SR (L), when supplied with a cross-circuit, transfers the image data given via the signal path K pixel by pixel to the sample-and-hold circuit SH (L). It is for import.

[Effect]

The circuit operation will be explained with reference to FIG. First, the operation when scanning lines are not thinned out will be described.

When eight pixel data belonging to one horizontal scanning line are supplied from signal path K, eight pixel data belonging to the same horizontal scanning line are supplied.
Of the pixel data, pixel ■. ■, 11 12 ■, ■ are taken into the sample hold circuit SH (U), and the pixels ■, ■, ■, ■ are taken into the sample hold circuit SH (U).
L). After that, if one scanning electrode (a) from the vertical scanning circuit VS is driven, one line of 8 pixels surrounded by a broken line is input from the signal path K to the IJ display device M. 8 belonging to l horizontal scanning line
pixel data can be displayed.

Next, an explanation will be given of the operation when one scanning line is thinned out from two scanning lines and displayed.

When 8 pixel data belonging to the first horizontal scanning line are supplied from the signal path K, the 8 pixel data belonging to the horizontal scanning line
Of the pixel data, pixels ■■, ■, ■ are taken into the sample and hold circuit SH (U), and the other pixels are discarded. Next, eight pixel data belonging to the second horizontal scanning line are supplied from the signal path K, and among the eight pixel data belonging to the horizontal scanning line, pixels ■, ■, ■, ■
is taken into the sample hold circuit SH (L), and other pixels are discarded. Under such a state, if one scanning electrode (a) from the vertical scanning circuit VS is driven, the signal is input from the signal path K to the l-line matrix display device M consisting of 8 pixels surrounded by a broken line. ■, ■, ■ of the pixels among the eight pixel data belonging to the first horizontal scanning line,
Pixels ■, ■, ■, and ■ among the eight pixel data belonging to the second horizontal scanning line can be displayed. In other words, the first and second two horizontal scanning lines are thinned out to one and displayed.

In this way, it is the same as taking the average of two vertically adjacent horizontal scanning lines, so one horizontal scanning line will not be completely missing, and discontinuities in the image will be noticeable. It becomes dull. Further, since the horizontal scanning lines can be displayed at the same position in the first field and the second field, it is possible to display a natural thinned-out image.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an embodiment of the scanning line number conversion image display device l3 l4 according to the present invention. Figure 1 shows a PAL image (hereinafter referred to as
By thinning out a PAL image (also simply called a PAL image) by 1 in 6 images, it can be displayed on a liquid crystal panel with 240 vertical pixels.1) A
FIG. 3 is a fucon diagram that does not show a device for reproducing L images.

The block diagram shown in FIG. 1 includes a signal circuit 7, a horizontal scanning circuit 14-1 . 14-2, a vertical scanning circuit (vertical shift register) 15, and a liquid crystal panel 18.

Further, the signal circuit 7 includes an input terminal l for a video signal (video).
, a synchronization separation circuit 2, a control circuit 3, a video signal processing circuit 4, a polarity switching circuit 5, and a thinning circuit 6, and the horizontal scanning circuit 14-1. 14-2 is liquid crystal panel l8
Horizontal shift 1 register 8-1 8
-2 and its shift clock, input terminal 1 for data signals, etc.
1-1. 11-2, Sample and hold circuit! 'J
-1, 9-2 and their three primary color RGB video signal input terminals 13-1. 13-2, n Hanwha amplifiers 10 for outputting sample and hold signals ] (consisting of 1-2 and OE terminals 111 and 122 for output control thereof).

The liquid crystal panels 18 are horizontally arranged vertically with each other.
0 horizontal signal electrodes 16-1 (n upper side, n lower side)
．． 16-2, in the scanning electrodes 17 of the vertical m tree, the drain and the gate I are selected 1 length, respectively, m x 2 n thin 1-simulated pixels 1-transistors (T Fi") 19,
and a liquid crystal pixel 20 connected to the source of each pixel transistor.

The operation of the circuit shown in FIG. 1 is as follows.

From the PAL video signal input to the input terminal 1, a synchronization separation circuit 2 separates horizontal and vertical 1υI signals. Based on this horizontal/vertical synchronizing signal, the control circuit 3 forms a control signal necessary for driving the horizontal scanning circuit 14-114-2, the vertical scanning circuit 15, and the polarity switching circuit 5.

On the other hand, in the video signal processing circuit 4, the input FA
I. Process the video signal to form the ROB primary color signal.

Note that in the case of a monochrome video signal instead of a color video signal, the video signal is a luminance signal, and the same is true.The present embodiment will be described below assuming color display.

After the polarity of the video signal is switched at regular intervals in the polarity switching circuit 5, it is applied to the sample and hold input terminals 13-1 and 132 of the horizontal scanning circuit 14-II4-2. Horizontal scanning circuit 14-1. 14-2 has input terminals 11-1. The horizontal shift registers 81 and 8-2 operate based on the signal inputted to the thinning circuit 11-2, and the sample and hold circuit 1-1 operates according to the outputs of the shift registers 81 and 8-2. , 9-2 is the terminal 13-1
．． At the same time as sampling the image signal applied to 13-2, the data is held for a predetermined period of time.

After sampling the image signal of one line (one horizontal scanning line), the outputs of the sample and hold circuits 9-l and 9-2 are sent to the sofa amplifiers 10-1. The input is 10-2,
The Hanwha Amplifier 10-1. The output of 10-2 is connected to its control terminal 12-1. 12-2, the scanning electrodes 16-1 . 16-2.

On the other hand, a vertical scanning circuit 15 composed of a shift register
Then, based on the signal from the control circuit 1 and the roll circuit 3 via the thinning circuit 6, for example, the clock is thinned out, the liquid crystal panel 1 is
8 m-tree scanning electrodes 17 are sequentially selectively driven. When the scanning electrode 17-i in the i-th row is driven, 2n transistors (19
-i, ]) to (19-i, 2n) are turned ON all at once. At this time, the control terminals 12-1 . In synchronization with the ○E signal applied to 12-2, the sample-and-hold image signal is output to the sample-and-hold circuits 9-1 and 9-2, and the pixel 1 run transistor (19-i, 1 ) ~ (19-i, 2n
) through liquid crystal pixels (20j, 1) to (20-i, 2n
) is written with a sampled image signal. That is,
Image information is written on the i-th line of the liquid crystal panel l8.

Hereinafter, the thinning circuit 6 in FIG. 1, which is an embodiment of the present invention, will be described.
The operation will be explained in detail.

FIG. 2 shows a waveform diagram of the main signals 17 ] 8 necessary for the circuit operation of FIG. 1. The signals shown in FIG. 2 are the horizontal synchronizing signal H sync applied to the control circuit 3,
The image signal R (red) is applied to the terminal 11-1, and the star 1 pulse ST of the horizontal shift register 8-1 is applied to the terminal 11-1.
H1 and its shift clock (corresponding to a sampling clock) CPHI, the start pulse STH2 of the horizontal shift register 8-2 applied to the terminal 112 and its shift clock CPH2, the start pulse STV of the vertical scanning circuit 15 and its shift clock CP■, terminal l2
Huffer amplifier 10-1 added to . 10-2 is the control signal OE.

Vertical scanning is started based on the rising edge of the vertical shift clock CPV when the start pulse STV of the shift register in the vertical scanning circuit 15 is input. In Figure 2,
The pulses of each related signal are given the same number. That is, the signal related to the first horizontal scanning period has the number 1, the second
Signals relating to the horizontal scanning period are numbered 2, . . . .

That is, vertical shift I occurs at the rise of CPV pulse 1.
- A scanning pulse is output from the first stage of the register 15,
The first scanning electrode 7-1 of the liquid crystal panel 18 is driven.

On the other hand, as a result of the pulses C of S TII1 and STH2 which are the same as the pulse l of Hsync approximately one horizontal period before the pulse 1 of CP■, the image signal R is transferred to the sample hold 9 (9-1, 9-2). Retained. This sampling data is approximately 1 horizontal scanning cycle faster than Hsyncl! Il
The control signal OE that rises after l causes the amplifier 10-1 . Output from 10-2, liquid crystal display 18
is written on the first line of The waveform of the signal electrode 16-1, 1 is the waveform 16-1, 1 of FIG. 2, and the signal electrode 16-2.
．． The waveform of 1 becomes waveform 16-2.1 in FIG.

In the decimation circuit 6 shown in FIG. 1, for example, as shown in FIG. (broken pulses are shown as dashed lines). At this time, STH
Since the pulse 6 of 1 is thinned out, the sample and hold circuit 9-1 does not sample 6 of the image signal R, and the data of 5 of the image signal R remains held.

On the other hand, in the sample hold circuit 9-2, S T
6 of the image signal R is sampled by the pulse 6 of H2. Further, the vertical shift register 15 does not operate at the time corresponding to pulse 5 of CPV, and remains stopped in the state of pulse 4 of CP■. The signal waveforms applied to the scanning electrodes 17 are as shown in 17-1 . 17-2
．． 17-3. 17-4. The sequential selection waveforms shown in 17-5 are obtained. That is, the state in which the fourth line of the liquid crystal panel 18 is selected continues during the CPV5 period.

At this time, since pulse 5 of the control signal OB has also stopped at the same time, there is no change in the contents of the pixels of the fourth line, and 4 of the image signal R continues. After the fifth line is selected by the CPV pulse, the OB pulse 6 outputs data 5 of the image signal R to the signal electrode 16-1, and data 6 of the image signal R to the signal electrode 16-2. Data is output. Therefore, signals No. 5 and No. 6 of the image signal R are alternately written into the pixels of the fifth line of the liquid crystal panel l8 and displayed simultaneously.

FIG. 3 shows the relationship between the scanning lines of the write signal displayed on the liquid crystal panel 18'2 by the thinning circuit 6 and the line numbers on the liquid crystal panel 18.

FIG. 3(a) shows the relationship between odd field display 3jJl. The liquid crystal panel 18 has 240 pixels in the vertical direction and can write 240 scanning lines. The scanning lines that can be written on the liquid crystal panel 18 are numbered and are written as panel line numbers on the left side of FIG. 3(a). On the other hand, the scanning line number of the image signal actually written is written on the liquid crystal panel 18 in FIG. 3(a).

According to the explanation of the waveform diagram in FIG.
By thinning out the vertical shift clock CPV and the horizontal sampling output control signal OE, the image signals for two scanning lines are horizontally distributed on one panel line, as shown in panel line number 5 in FIG. 3(a). In other words, the averaged signals of two adjacent scanning lines of 21 22 are displayed, and 6
Image signals are written to the book at a rate of 5 trees.

As a result of this, Figure 3 (aH, as shown, LCD panel 1
87 is written with an image signal in which one scanning line is interrogated in 6 trees, so on the cryo-crystal panel 18, which consists of 240 lines, originally from the 1st line to 287 lines are written. 287
An image of an odd field consisting of tree scanning lines is displayed in a vertically reduced state.

Similarly, even in the even field shown in FIG. 3(b), the LCD panel 18 displays an even-numbered screen consisting of 287 scanning lines from the 313th tree to the 599th tree, vertically. Displayed in a reduced size.

FIG. 4 shows a thinning relationship that aims at a more natural display than the thinning relationship shown in FIG. In FIG. 3, the order of the two write signal scanning line numbers written to one panel line of the liquid crystal panel 18 is such that the smallest number is on the left in both the odd and even fields. That is, 1
In a frame, image signals at the same position are thinned out. On the other hand, in FIG. 4, the above order is changed between odd numbered fields l and even numbered fields j, so that the thinning becomes even.

In this case, start pulse ST1-1 in Fig. 2
It is necessary to thin out S ′FI1 2 instead of 1. ″
In other words, the start pulses S T H I to S T'
When either H2 is decimated, the other Star 1 pulse is not decimated.

Therefore, according to the invention shown in FIG. 4, image discontinuity becomes less noticeable, and a PAL image can be displayed more naturally with an aspect ratio of 43 on the liquid paper 18 with an aspect ratio of 1 and a ratio of 4:3. Therefore, the effect of the wooden invention is clear.

FIG. 5 shows a specific circuit configuration example of the thinning circuit 6 in FIG. 1. The circuit shown in FIG. 5 can be roughly divided into two blocks. One is the thinning pulse generation circuit 21 and the other is the K-I circuit 37.

The thinning pulse generation circuit 21 includes a counter 25, a timing adjustment circuit 26. 27. He was fired on the 28th. Power·
The synchronizer 23 24 counts, for example, Hsync (horizontal synchronization signal) every six, which is input to the terminal 24, based on the STV (start pulse ■) input to the terminal 23 as a reference. That is, the counter 25 generates a pulse every six Hsyncs.

Based on this pulse, the timing adjustment circuit 26 generates a pulse of negative polarity that shifts pulse 5 (dashed line) of CI)V in FIG. 2, and the timing adjustment circuit 27 shifts pulse 5 (dashed line) of OE. Generates a pulse of negative polarity,
The timing adjustment circuit 28 generates a pulse of positive polarity that overrides the pulse 6 (broken line) of S T H1.

As shown in FIG. 6, the timing adjustment circuit includes a delay circuit 5.
7 and a monostable multi-bi break 58, the pulse input to the terminal 594 is delayed for a certain period of time by the delay circuit 57, and then the monostable multi-high break 58 forms a constant width pulse, which is output from the terminal 60. Cheating.

Game 1 circuit 37 consists of four AND circuits and two NAN circuits.
It consists of a D circuit and one inheritor circuit.

The AND 33 gates the CP■ input to the terminal 30 with the thinning pulse from the timing adjustment circuit 26.

Furthermore, since the thinning pulses from the tie adjustment circuit 26 are of negative polarity, the pulses of CP■ input to the terminal 30 are thinned out at a ratio of one in six, and are output from the terminal 7-38. .

Similarly, in AND34, OE input to terminal 31
The pulses are also thinned out at a rate of 1 every 64+1J in the AND 34 and outputted from the terminal 39. NAND57
Now, based on the field discrimination signal FI], in the life number field or the even number field, the positive polarity pulse of the timing adjustment circuit 28 is output with negative polarity.

According to this pulse, the AND 35 thins out the STH pulses input to the terminal 7-32 at a ratio of one in six, and outputs it to the terminal 40 as STH 1. Similarly,
NANI) 58 outputs the positive pulse of the timing ljJ adjustment circuit 28 with negative polarity in a field different from that of the NAND 57 based on the output of the inharter 29 to which the field discrimination signal FD is input.

In the 25 26 AND 36, according to this pulse, the S T H pulses input to the terminal 32 are thinned out at a ratio of 1 in 6 pulses and outputted to the terminal 41 as S T I-1 2. Note that the field discrimination signal FD is derived from the vertical synchronizing signal, and has a period twice that of the vertical synchronizing signal.

FIG. 7 shows a second embodiment of the invention. The difference from the first embodiment shown in FIG. 1 is that signals for two horizontal scanning lines are averaged in an analog manner, and the signals are averaged for one line. For this purpose, the circuit configuration is such that a circuit 44 surrounded by a broken line is inserted between the video signal processing circuit 4 and the polarity switching circuit 5, as shown in FIG.

There is an analog switch 43 within the broken line 44, and by switching this switch, it is selected whether to output the output signal 45 of the video signal processing circuit 4 or the output signal 49 of the averaging circuit. Switching of the analog switch 43 is performed by a control signal 5l of the thinning circuit 106.

The averaging circuit has the configuration shown in FIG. Delay circuit 4
8 has a delay amount of one horizontal period. 46 is an adder, 47
is a 6 dB attenuator (voltage '/2). That is, the output of the averaging circuit 49 is the signal average value for j2 rows per horizontal scanning period.

The operation in FIG. 7 will be explained using the waveform diagram in FIG. 9. However, the synchronization separation circuit 2, control circuit 3, video signal processing circuit (video chroma circuit) 4, and polarity switching circuit 5 are
Since this is the same as that in the embodiment, it will not be specifically explained here.

The signals switched by the analog switch 43 are the output 45 of the video signal processing circuit 4 and the output 49 of the averaging circuit. As already explained, 49 is the average value of two lines, and in the meaning of expressing it, (1+2)(2+3).・・・
...is written on the waveform diagram. The signal that controls switching of the analog switch is the output 51 of the thinning circuit 106.
It is. During the period when 5l is positive polarity, the input 50 of the polarity switching circuit 5 is the output signal 45 of the video signal processing circuit 4, and during the period when 51 is negative polarity, the input 50 is the output 49 of the averaging circuit 42. .

That is, during the period in which the control signal 5l has negative polarity, for example (
5+6) is selected and sampled and held by STH27286. This sampled and held data is output to the signal electrode 116 and written to the liquid crystal panel 118 in synchronization with the OE pulse 6.

Of course, in the vertical scanning circuit l5, as in the first embodiment,
Control is performed by thinning out pulses 5 of CP■. In addition, by thinning out pulse 5 of OE, S
Writing of the image signal 5 sampled and held by the TH pulse 5 is prohibited. Therefore, the signal 116 written to the liquid crystal panel is 1 2 3, 4, (5+6)
, 7...

A third embodiment of the invention is shown in FIG. FIG. 10 is characterized in that in some rows of the liquid crystal panel 218, there are two gate lines for one row of pixels in the horizontal direction. Here, the pixel 55 in FIG. 10 may be considered to be equivalent to the combination of the pixel transistor 19 and the liquid crystal pixel 20 in FIG.

The two gate lines assigned to one row are, for example, 55-
Gate lines 217-5, 217-6 for 5 rows of pixels
It is arranged like this. That is, 55-5.1, 55-5.3, 55-5, (2n-
1) is connected to the gate line 217-5, and the remaining pixels 555,2, 55-5.4, 55-5, (2n)
is connected to the gate 1 to line 2176. Vertical scanning circuit 21
5, a shift 1 resistor is formed of the same number of Frisopfrons 53 as gate lines, and a Huffer amplifier 52 drives the gate 217.

The gate lines 217-5 and 217-6 are selected by the switch 56 to be selected simultaneously or sequentially. this is,
Flip-flops 53-4 and 53-5 simultaneously receive data 54-4 of 53-4, or 53-4, 53-5
The difference is whether they are received sequentially or not.

Therefore, when the gate lines 217-5 and 217-6 are selected at the same time, a television signal system display having the same number of horizontal scanning lines as the number of horizontal pixels of the liquid crystal panel 218 can be performed. Also,
If the gate lines 217-5 and 217-6 are selected sequentially, the same effect as in the first embodiment can be obtained.

In this third embodiment, thinned-out display is possible simply by switching the switch 56.

29 30 A fourth embodiment of the present invention is shown in FIG. The feature of the fourth embodiment is the liquid crystal panel 318. In the third embodiment, two gate lines are arranged in some rows, but the fourth
In the example, we created a two-tree game line {=t JJII L over all rows. Two games 1/Line arrangement 6
, L have been described above, so they will not be discussed here.

Also, in the vertical direction, one pixel corresponds to two pixels next to each other.
Route 3 has been placed. For example, pixels 55-Ll and 55-1
, 2 are arranged with common signal lines.

As a result, even if either pixel 55-Ll or 55-L2 is damaged, as long as the other one is intact, v
Display in the L1 row and vertical column becomes possible.

The differences from FIG. 1 are the structure of the liquid crystal panel 318, the arrangement of the horizontal scanning circuit 14, the arrangement of the vertical scanning circuit 15, and the thinning circuit. One horizontal scanning circuit l4 was arranged above the liquid crystal panel 318, and one vertical scanning circuit 15 was arranged on both the left and right sides of the liquid crystal panel 318.

The operation shown in FIG. 1l will be explained based on the waveform diagram shown in FIG. 12. The horizontal synchronization signal Hsync, the image signal R, the star I pulse S ``r'' II of the horizontal shift 1 register and its shift 1 clock C PH, the start pulse STV of the vertical shift register, and the OE signal for output control have already been explained. I've already mentioned it, so I won't explain it here.

CPV 1 is the shift 1 clock of the vertical shift 1 register in the vertical scanning circuit l5-1, CPV 2 1
=;1 Vertical shift caused by the vertical scanning circuit 15-2 - Shift clock of the register. Also, does M1 control the output of the vertical scanning circuit 15-1? MII cheat signal, M
When 1 is negative polarity, the output of the vertical scanning circuit 15-1 is prohibited, and the gate 1 line is also not selected. Similarly, M2 is an output control signal of the vertical scanning circuit 15-2.

In order to obtain the same effect as in the first embodiment, here, CP
Thin out V1 and CPV2. For example, Figure 12 CPV1
By thinning out the pulse 6 of CPV2 and the pulse 5 of CPV2, the GEL lines 17 2.4 and 17-2.5 become waveforms including the broken lines in FIG. Furthermore, due to the Ml signal, 1
7-1, 5 broken line part from M2 signal 6, 17-2
, /I are controlled by the broken lines. 17-2.
4, 17-L5 is shown as a solid line.

31 32 At this time, first, the fourth row of the liquid crystal panel 318 is connected to the gate line 1.
7-1, 5, and 17-2.4 are simultaneously selected, and signal 4 on signal line 16 is written. Next, gate line signal 17
-1,5 makes the odd numbered pixel in the 5th row (555+l
, 55-5+3...) is selected, and the signal line 16
Signal 5 is written, and gate line signal 17-2.
5, the even numbered pixel in the 5th row (55-5.2, 5
55, 4, . . .), the signal 6 of the signal line 16 is written.

Therefore, the effects of the present invention can be obtained.

A fifth embodiment of the present invention is shown in FIG. In this embodiment, as detailed in Japanese Patent Application Laid-Open No. 63-26084, a video signal of one horizontal scanning period is sampled, and two adjacent rows of pixels are sampled in the first half and second half of the subsequent one horizontal scanning period. This is an example in which the present invention is applied to double-speed line sequential scanning in which the 3D images are driven separately.

FIG. 15 has basically the same circuit configuration as FIG. 1. The difference is that only the vertical scanning circuit 315 is controlled by the signal from the thinning circuit 306, and the horizontal scanning circuit 214 is controlled by the signal from the thinning circuit 306.
is a point where no special control by thinning is performed.

A detailed block diagram of the thinning circuit 306 is shown in FIG.

The basic configuration is also the same as that shown in FIG. 5, and the tying adjustment circuits 126 and 127 are as shown in FIG. Therefore, detailed explanation of the circuit operation will be omitted.

FIG. 16 is a diagram for explaining FIG. 15, and shows the relationship between panel line numbers and write signal scanning line numbers in the liquid crystal panel 418.

FIG. 18 is a diagram of main signal waveforms in FIGS. 15 and 17. In the double-speed line sequential scanning described above, in either the first field or the second field, normally, that is, when no thinning is performed, two adjacent lines are scanned in the same manner as shown in FIG. 16(a). A line signal is written.For example, write signal scanning line number 2 is written to bar line numbers 3 and 4.
signal is written. And the other feel I.
In this case, the combination of panel line numbers is shifted, and the signals of the same scanning line are written in two adjacent lines.

For example, the write scan line signal 2 is written to panel line numbers 2 and 3.

33 34 When the thinning operation of the present invention is performed in this double-speed line sequential scanning, the result is as shown in FIG. 16(b).

That is, the signals of write signal scanning line numbers 5 and 6 written in panel line numbers 10 and 11 shown in FIG. 16(a) are thinned out, and the signals of write signal scanning line numbers 5 and 6 written in panel line numbers 10 and 11 shown in FIG. Write signal scanning line numbers 5 and 6 are written in two rows numbered 9 and 10. Thereby, in double-speed line sequential scanning, it is possible to take the average of two adjacent horizontal scanning lines.

The thinning operation of the fifth embodiment will be explained based on the main signal waveform diagram shown in FIG. In double-speed line sequential scanning, the first
The period of the shift clock CPV of the vertical scanning circuit 315 in FIG. 5 is half the period of H sync. Furthermore, the control signal ○E also has a cycle that is half of H sync. Therefore, for example, by the pulse 2-1 of CP■, the signal line 3
17-3 is selected, and the image signal 2-1 on the signal line 217 is input to the pixel selected on the signal line 317-3 by the pulse 2-1 of OE.

Similarly, the image signal 2-2 of the signal vA217 is written into the pixel selected by the signal line 317-4. That is, panel line number 3 of the liquid crystal panel 418 in FIG.
The signal of the write scanning line number 2 is written in the two rows 4 and 4.

Attention is now paid to CPV pulses 5-2 and 61 in FIG. These pulses are decimated by a decimation circuit 306, as shown by the dashed line. Therefore, the output of the signal line 317-9 has a combination of a solid line and a broken line. Furthermore, by controlling the output of the vertical scanning circuit with the M signal, the output of the signal line 31710 becomes the same as the solid line.

At this time, the pixel selected by the signal line 317-9 has OE
The image signal 5-1 of the signal line 217 is written by the pulse 5-1 of the signal line 217, and the image signal 6-1 of the signal line 217 is written by the pulse 6-2 of the OE to the pixel selected by the signal line 317-10.
2 image signals are written. That is, Fig. 16 (b
), the image signal 5 is input to and output from the panel line number 9 of the liquid crystal panel 418, and the image signal 6 is written to the panel line number 10.

〔Effect of the invention〕

As described above, according to the present invention, by thinning l rows on average from signals for two rows of adjacent horizontal scanning periods, the number of scanning lines can be increased without completely losing one of the two rows. This has the advantage that an image with a larger number of scanning lines can be displayed naturally on a display panel with a smaller number of display scanning lines, with less discontinuity.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a signal waveform diagram of the main part thereof, and Figs. 3 and 4 respectively show panel line numbers and display image signals related to the present invention. 5 is a circuit diagram showing a specific example of the thinning circuit in FIG. 1, FIG. 6 is a block diagram showing an example of the configuration of the main part in FIG. 5, and FIG. 8 is a block diagram showing another embodiment of the present invention, FIG. 8 is a circuit diagram showing a specific example of the averaging circuit in FIG. 7, FIG. 9 is a signal waveform diagram of the main part in FIG. 7, and FIG. 11 is a professional diagram showing another embodiment of the present invention, FIG. 12 is a signal waveform diagram of the main part in FIG. 11, and FIG.
4 is an explanatory diagram showing the relationship between panel line numbers and scanning lines of display image signals in connection with embodiments of the present invention, and FIG. 15 is a block diagram showing still another embodiment of the present invention. FIG. 16 is an explanatory diagram showing the relationship between panel line numbers and scanning lines of display image signals in connection with the embodiment of the present invention;
FIG. 17 is a block diagram showing a configuration example of the main parts in FIG. 15, FIG. 18 is a signal waveform diagram of the main parts in FIG. 15, and FIG. 19 is a basic diagram of means for solving the problems of the present invention. FIG. 2 is a conceptual diagram showing the configuration. Code explanation 1...Video input terminal, 2...Synchronization separation circuit, 3.
...Control circuit, 4...Video signal processing circuit, 5
... Polarity switching circuit, 6... Thinning circuit, 14... Horizontal scanning circuit, 15... Vertical scanning circuit, l8... Liquid crystal panel, 43. 56... switch, 48. 5
7... Delay circuit, 58... Monostable multi-bicycle 37 38 ntn

Claims (1)

[Claims] 1. A matrix display panel having a number of pixels sufficient to display a video signal having a first number of scanning lines, and a second matrix display panel having a number of pixels greater than the first number of scanning lines. When a video signal having a number of scanning lines is to be displayed on the matrix display panel, the number of scanning lines is reduced by thinning out the number of scanning lines from the second number of scanning lines. In the converted image display device, a plurality of scanning electrodes (17-1 to 17-m) extending in one direction
, a plurality of signal electrodes (
16-1, 1-16-1, n: 16-2, 1-16-2
, n) and display elements (20-1, 1 to 20-m, 2n) arranged and connected in a matrix at their intersections; and the plurality of signal electrodes (16-1, 1-16-1, n:1
6-2, 1 to 16-2, n) are divided into a plurality of groups, and a horizontal scanning circuit (14-1, 14-2) with a sample and hold circuit connected to each group for each group; When displaying a video signal having the first number of scanning lines, each of the plurality of sets of horizontal scanning circuits (14-1, 14-2) A drive signal for driving the vertical scanning circuit (15) once after capturing and holding image information belonging to the same scanning line is supplied to the sample and hold circuit, and a second scanning line whose number is greater than the first scanning line is supplied. When displaying a video signal having a number of scanning lines, the plurality of sets of horizontal scanning circuits (14-1, 14-
a drive signal supply circuit (6) for supplying a drive signal for driving the vertical scanning circuit (15) once after capturing and holding image information belonging to different scanning lines to each sample and hold circuit in 2); 1. A scanning line number conversion image display device comprising: 2. A matrix display panel having a plurality of scanning electrodes extending in one direction and a plurality of signal electrodes extending in a direction crossing the one direction, and display elements arranged and connected at the intersection points thereof;
In a matrix display device comprising a vertical scanning circuit connected to the scanning electrode and a horizontal scanning circuit connected to the signal electrode, the input video signal to be displayed and the input video signal one horizontal scanning period before the input video signal are an averaging circuit that takes and outputs an average; a drive signal supply source that outputs a drive control signal that causes the vertical scanning circuit to intermittent its sequential selection operation; and an input video signal and an averaged output signal from the averaging circuit. 1. A scanning line number conversion image display device comprising: a switch circuit for switching and inputting the signal to the horizontal scanning circuit in synchronization with the intermittent operation in the vertical scanning circuit. 3. A matrix display panel having a plurality of scanning electrodes extending in one direction and a plurality of signal electrodes extending in a direction crossing the one direction, and display elements arranged and connected at the intersection points thereof;
In a matrix display device comprising a vertical scanning circuit connected to the scanning electrode and a horizontal scanning circuit connected to the signal electrode, all the display elements in one direction and one row in the matrix display panel are one and the same. a row connected to the scanning electrode of
In one direction, rows in which each of the display elements constituting one row is alternately connected to two adjacent scanning electrodes are placed in the matrix display panel in a mixed manner, and in the vertical scanning circuit, the adjacent scanning electrodes are 1. A scanning line number conversion image display device comprising a switch for selecting and driving two scanning electrodes simultaneously or sequentially. 4. A matrix display panel having a plurality of scanning electrodes extending in one direction and a plurality of signal electrodes extending in a direction crossing the one direction, and display elements arranged and connected at the intersection points thereof;
In a matrix display device comprising a vertical scanning circuit connected to the scanning electrode and a horizontal scanning circuit connected to the signal electrode, each of the plurality of scanning electrodes has a first scanning electrode and a second scanning electrode. A plurality of pairs of scan electrodes are configured, each of the display elements constituting one row in one direction in the matrix display panel is alternately connected to the adjacent pair of scan electrodes; A simultaneous sequential selection waveform is applied to some of the pair of scanning electrodes connected to the display elements constituting one row in one direction from the vertical scanning circuit, so that one row in one direction is The vertical scanning circuit applies sequential selection waveforms that are shifted by one horizontal scanning period to the remaining scanning electrodes in the pair of scanning electrodes connected to the constituent display elements. 1. A scanning line number conversion image display device comprising a drive signal source for driving a vertical scanning circuit. 5. A matrix display panel having a plurality of scanning electrodes extending in one direction and a plurality of signal electrodes extending in a direction crossing the one direction, and display elements arranged and connected at the intersection points thereof;
In a matrix display device comprising a vertical scanning circuit connected to the scanning electrode and a horizontal scanning circuit with a sample and hold circuit connected to the signal electrode, the scanning electrodes are sequentially shifted by 1/2 horizontal scanning period. A number of scanning lines characterized by comprising a drive signal source that drives with a selected waveform and a clock source that can thin out and output two consecutive shift clocks that drive the vertical scanning circuit. Conversion image display device. 6. A matrix display panel having a plurality of scanning electrodes extending in one direction and a plurality of signal electrodes extending in a direction crossing the one direction, and display elements arranged and connected at the intersection points;
In a matrix display device comprising a vertical scanning circuit connected to the scanning electrode and a horizontal scanning circuit connected to the signal electrode, each display element in one direction and one row in the matrix display panel is composed of one and the same display element. Rows that display image signals belonging to a horizontal scanning period and rows that alternately display image signals belonging to two adjacent horizontal scanning periods in one direction, in which each of the display elements constituting one row are mixed. A scanning line number conversion image display device characterized by displaying on the matrix display panel.