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IT1031886B - Procedimento di elettroplaccatura selettiva di oro su una regione di metallo nobile di una superficie composita - Google Patents

Procedimento di elettroplaccatura selettiva di oro su una regione di metallo nobile di una superficie composita

Info

Publication number
IT1031886B
IT1031886B IT2045275A IT2045275A IT1031886B IT 1031886 B IT1031886 B IT 1031886B IT 2045275 A IT2045275 A IT 2045275A IT 2045275 A IT2045275 A IT 2045275A IT 1031886 B IT1031886 B IT 1031886B
Authority
IT
Italy
Prior art keywords
gold
procedure
region
noble metal
composite surface
Prior art date
Application number
IT2045275A
Other languages
English (en)
Original Assignee
Western Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US443624A external-priority patent/US3926747A/en
Priority claimed from US443625A external-priority patent/US3873428A/en
Application filed by Western Electric Co filed Critical Western Electric Co
Application granted granted Critical
Publication of IT1031886B publication Critical patent/IT1031886B/it

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00Electroplating: Baths therefor
    • C25D3/02Electroplating: Baths therefor from solutions
    • C25D3/48Electroplating: Baths therefor from solutions of gold
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02Electroplating of selected surface areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
    • H01L23/485Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes) consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/24Reinforcing the conductive pattern
    • H05K3/241Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/24Reinforcing the conductive pattern
    • H05K3/243Reinforcing the conductive pattern characterised by selective plating, e.g. for finish plating of pads
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/24Reinforcing the conductive pattern
    • H05K3/244Finish plating of conductors, especially of copper conductors, e.g. for pads or lands

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Organic Chemistry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electrochemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Manufacturing & Machinery (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Electroplating And Plating Baths Therefor (AREA)
IT2045275A 1974-02-19 1975-02-19 Procedimento di elettroplaccatura selettiva di oro su una regione di metallo nobile di una superficie composita IT1031886B (it)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US443624A US3926747A (en) 1974-02-19 1974-02-19 Selective electrodeposition of gold on electronic devices
US443625A US3873428A (en) 1974-02-19 1974-02-19 Preferential gold electroplating

Publications (1)

Publication Number Publication Date
IT1031886B true IT1031886B (it) 1979-05-10

Family

ID=27033593

Family Applications (1)

Application Number Title Priority Date Filing Date
IT2045275A IT1031886B (it) 1974-02-19 1975-02-19 Procedimento di elettroplaccatura selettiva di oro su una regione di metallo nobile di una superficie composita

Country Status (7)

Country Link
JP (1) JPS5440056B2 (it)
DE (1) DE2506990C3 (it)
FR (1) FR2261352B1 (it)
GB (1) GB1494394A (it)
IT (1) IT1031886B (it)
NL (1) NL160034C (it)
SE (1) SE446751B (it)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4226167C2 (de) * 1992-08-07 1996-10-24 Sel Alcatel Ag Verfahren zum elektrisch leitenden Verbinden unter Anwendung der Flipchip-Technik
KR20000076081A (ko) * 1997-03-10 2000-12-26 야마모토 카즈모토 반도체 장치의 배선 형성 방법 및 반도체 장치

Also Published As

Publication number Publication date
NL160034B (nl) 1979-04-17
GB1494394A (en) 1977-12-07
DE2506990A1 (de) 1975-08-28
SE446751B (sv) 1986-10-06
DE2506990B2 (de) 1979-01-25
NL7501908A (nl) 1975-08-21
NL160034C (nl) 1979-09-17
SE7501777L (it) 1975-08-20
JPS5440056B2 (it) 1979-12-01
JPS50124841A (it) 1975-10-01
DE2506990C3 (de) 1979-09-13
FR2261352A1 (it) 1975-09-12
FR2261352B1 (it) 1978-04-21

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