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FR3089681B1 - Mémoire à lecture unique - Google Patents

Mémoire à lecture unique Download PDF

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Publication number
FR3089681B1
FR3089681B1 FR1872645A FR1872645A FR3089681B1 FR 3089681 B1 FR3089681 B1 FR 3089681B1 FR 1872645 A FR1872645 A FR 1872645A FR 1872645 A FR1872645 A FR 1872645A FR 3089681 B1 FR3089681 B1 FR 3089681B1
Authority
FR
France
Prior art keywords
read memory
single read
memory
circuit
memory cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1872645A
Other languages
English (en)
Other versions
FR3089681A1 (fr
Inventor
Michael Peeters
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Proton World International NV
Original Assignee
Proton World International NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Proton World International NV filed Critical Proton World International NV
Priority to FR1872645A priority Critical patent/FR3089681B1/fr
Priority to US16/708,316 priority patent/US11049567B2/en
Publication of FR3089681A1 publication Critical patent/FR3089681A1/fr
Application granted granted Critical
Publication of FR3089681B1 publication Critical patent/FR3089681B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/22—Safety or protection circuits preventing unauthorised or accidental access to memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/32—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1695—Protection circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0059—Security or protection circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
    • G11C2216/22—Nonvolatile memory in which reading can be carried out from one memory bank or array whilst a word or sector in another bank or array is being erased or programmed simultaneously
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Read Only Memory (AREA)

Abstract

Mémoire à lecture unique La présente description concerne un circuit mémoire (7) comportant : au moins une cellule mémoire non volatile réinscriptible (72) ; et un circuit (76) d'effacement de la cellule mémoire à réception d'une requête en lecture. Figure pour l'abrégé : Fig. 6
FR1872645A 2018-12-10 2018-12-10 Mémoire à lecture unique Active FR3089681B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR1872645A FR3089681B1 (fr) 2018-12-10 2018-12-10 Mémoire à lecture unique
US16/708,316 US11049567B2 (en) 2018-12-10 2019-12-09 Read-once memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1872645A FR3089681B1 (fr) 2018-12-10 2018-12-10 Mémoire à lecture unique

Publications (2)

Publication Number Publication Date
FR3089681A1 FR3089681A1 (fr) 2020-06-12
FR3089681B1 true FR3089681B1 (fr) 2021-08-06

Family

ID=66641032

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1872645A Active FR3089681B1 (fr) 2018-12-10 2018-12-10 Mémoire à lecture unique

Country Status (2)

Country Link
US (1) US11049567B2 (fr)
FR (1) FR3089681B1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11467954B2 (en) 2020-10-03 2022-10-11 Lenovo (Singapore) Pte. Ltd. Passing data between programs using read-once memory

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3764986A (en) 1972-08-09 1973-10-09 Mi2 Columbus Magnetic tape data processing system
JP3553786B2 (ja) 1998-03-13 2004-08-11 松下電器産業株式会社 半導体集積回路装置およびその製造方法
FR2823364B1 (fr) 2001-04-05 2003-06-27 St Microelectronics Sa Dispositif et procede de protection partielle en lecture d'une memoire non volatile
US7218567B1 (en) * 2005-09-23 2007-05-15 Xilinx, Inc. Method and apparatus for the protection of sensitive data within an integrated circuit
KR20110052941A (ko) 2009-11-13 2011-05-19 삼성전자주식회사 어디티브 레이턴시를 가지는 반도체 장치
US8509003B2 (en) * 2011-09-20 2013-08-13 Taiwan Semiconductor Manufacturing Co., Ltd. Read architecture for MRAM
JP2013122797A (ja) * 2011-12-09 2013-06-20 Toshiba Corp 半導体記憶装置
US8717831B2 (en) 2012-04-30 2014-05-06 Hewlett-Packard Development Company, L.P. Memory circuit
KR101991905B1 (ko) * 2012-07-19 2019-06-24 삼성전자주식회사 불휘발성 메모리, 불휘발성 메모리의 읽기 방법 및 불휘발성 메모리를 포함하는 메모리 시스템
TW201417102A (zh) * 2012-10-23 2014-05-01 Ind Tech Res Inst 電阻式記憶體裝置
US9230622B2 (en) 2012-11-30 2016-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Simultaneous two/dual port access on 6T SRAM
JP6012876B2 (ja) 2013-08-22 2016-10-25 ルネサスエレクトロニクス株式会社 ツインセルの記憶データをマスクして出力する半導体装置
US9262256B2 (en) 2013-12-24 2016-02-16 Intel Corporation Using dark bits to reduce physical unclonable function (PUF) error rate without storing dark bits location
US10115467B2 (en) * 2014-09-30 2018-10-30 Jonker Llc One time accessible (OTA) non-volatile memory
US10839086B2 (en) * 2014-09-30 2020-11-17 Jonker Llc Method of operating ephemeral peripheral device
US9881687B2 (en) * 2015-12-18 2018-01-30 Texas Instruments Incorporated Self-latch sense timing in a one-time-programmable memory architecture
US20170344295A1 (en) * 2016-05-31 2017-11-30 Sandisk Technologies Llc System and method for fast secure destruction or erase of data in a non-volatile memory
KR102491358B1 (ko) * 2016-11-22 2023-01-26 매그나칩 반도체 유한회사 센스 앰프 구동 장치
US10242747B1 (en) * 2017-12-28 2019-03-26 Micron Technology, Inc. Charge loss failure mitigation

Also Published As

Publication number Publication date
US11049567B2 (en) 2021-06-29
FR3089681A1 (fr) 2020-06-12
US20200185037A1 (en) 2020-06-11

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