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FR3091018B1 - Mémoire de puce électronique - Google Patents

Mémoire de puce électronique Download PDF

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Publication number
FR3091018B1
FR3091018B1 FR1873830A FR1873830A FR3091018B1 FR 3091018 B1 FR3091018 B1 FR 3091018B1 FR 1873830 A FR1873830 A FR 1873830A FR 1873830 A FR1873830 A FR 1873830A FR 3091018 B1 FR3091018 B1 FR 3091018B1
Authority
FR
France
Prior art keywords
microchip memory
memory
cell
microchip
doped semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1873830A
Other languages
English (en)
Other versions
FR3091018A1 (fr
Inventor
Stéphane Denorme
Philippe Candelier
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics France SAS
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Priority to FR1873830A priority Critical patent/FR3091018B1/fr
Priority to US16/708,912 priority patent/US11355503B2/en
Priority to CN201911336484.6A priority patent/CN111352895B/zh
Priority to CN201922328679.8U priority patent/CN211062473U/zh
Publication of FR3091018A1 publication Critical patent/FR3091018A1/fr
Application granted granted Critical
Publication of FR3091018B1 publication Critical patent/FR3091018B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G06F15/781—On-chip cache; Off-chip memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/75—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
    • G06F21/79—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/22—Safety or protection circuits preventing unauthorised or accidental access to memory cells
    • G11C16/225—Preventing erasure, programming or reading when power supply voltages are outside the required ranges
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/148—Details of power up or power down circuits, standby circuits or recovery circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
    • H10B20/25—One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/518—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their lengths or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Software Systems (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Geometry (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

Mémoire de puce électronique La présente description concerne un dispositif (300) comprenant : au moins trois cellules mémoire (110) ; pour chaque cellule, une première région semiconductrice dopée (234) et un interrupteur (120) reliant la cellule à la première région ; et des premières zones semiconductrices dopées (302) connectant ensemble les premières régions (234). Figure pour l'abrégé : Fig. 3
FR1873830A 2018-12-21 2018-12-21 Mémoire de puce électronique Active FR3091018B1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
FR1873830A FR3091018B1 (fr) 2018-12-21 2018-12-21 Mémoire de puce électronique
US16/708,912 US11355503B2 (en) 2018-12-21 2019-12-10 Electronic chip memory
CN201911336484.6A CN111352895B (zh) 2018-12-21 2019-12-23 电子芯片存储器
CN201922328679.8U CN211062473U (zh) 2018-12-21 2019-12-23 器件和存储器

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1873830A FR3091018B1 (fr) 2018-12-21 2018-12-21 Mémoire de puce électronique

Publications (2)

Publication Number Publication Date
FR3091018A1 FR3091018A1 (fr) 2020-06-26
FR3091018B1 true FR3091018B1 (fr) 2023-01-20

Family

ID=66867292

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1873830A Active FR3091018B1 (fr) 2018-12-21 2018-12-21 Mémoire de puce électronique

Country Status (3)

Country Link
US (1) US11355503B2 (fr)
CN (2) CN211062473U (fr)
FR (1) FR3091018B1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114068689B (zh) * 2022-01-12 2022-04-01 深圳大学 基于栅极外悬量调制晶体管的新型熵源结构及其制造方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4829017A (en) * 1986-09-25 1989-05-09 Texas Instruments Incorporated Method for lubricating a high capacity dram cell
US6798693B2 (en) * 2001-09-18 2004-09-28 Kilopass Technologies, Inc. Semiconductor memory cell and memory array using a breakdown phenomena in an ultra-thin dielectric
US6766960B2 (en) * 2001-10-17 2004-07-27 Kilopass Technologies, Inc. Smart card having memory using a breakdown phenomena in an ultra-thin dielectric
US7528015B2 (en) * 2005-06-28 2009-05-05 Freescale Semiconductor, Inc. Tunable antifuse element and method of manufacture
US7772632B2 (en) * 2006-08-21 2010-08-10 Micron Technology, Inc. Memory arrays and methods of fabricating memory arrays
JP5078338B2 (ja) * 2006-12-12 2012-11-21 ルネサスエレクトロニクス株式会社 半導体記憶装置
FR2990291A1 (fr) * 2012-05-03 2013-11-08 St Microelectronics Sa Procede de controle du claquage d'un antifusible
JP2015026998A (ja) * 2013-07-26 2015-02-05 株式会社東芝 マルチコンテキストコンフィグレーションメモリ
FR3021806B1 (fr) * 2014-05-28 2017-09-01 St Microelectronics Sa Procede de programmation d'une cellule memoire non volatile comprenant une grille de transistor de selection partagee
US10170625B2 (en) * 2017-01-20 2019-01-01 Globalfoundries Singapore Pte. Ltd. Method for manufacturing a compact OTP/MTP technology
US9953990B1 (en) * 2017-08-01 2018-04-24 Synopsys, Inc. One-time programmable memory using rupturing of gate insulation
KR20190122421A (ko) * 2018-04-20 2019-10-30 삼성전자주식회사 반도체 소자
KR102523714B1 (ko) * 2019-01-21 2023-04-20 삼성전자주식회사 메모리 장치
US10818330B2 (en) * 2019-01-31 2020-10-27 Avalanche Technology, Inc. Fast programming of magnetic random access memory (MRAM)
US11170852B1 (en) * 2020-06-24 2021-11-09 Sandisk Technologies Llc Cross-bar arrays having steering element with diode

Also Published As

Publication number Publication date
US11355503B2 (en) 2022-06-07
US20200203356A1 (en) 2020-06-25
CN211062473U (zh) 2020-07-21
CN111352895A (zh) 2020-06-30
CN111352895B (zh) 2025-02-21
FR3091018A1 (fr) 2020-06-26

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