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FR2365179A1 - Dispositif pour realiser l'adressage d'une memoire mos - Google Patents

Dispositif pour realiser l'adressage d'une memoire mos

Info

Publication number
FR2365179A1
FR2365179A1 FR7727200A FR7727200A FR2365179A1 FR 2365179 A1 FR2365179 A1 FR 2365179A1 FR 7727200 A FR7727200 A FR 7727200A FR 7727200 A FR7727200 A FR 7727200A FR 2365179 A1 FR2365179 A1 FR 2365179A1
Authority
FR
France
Prior art keywords
conductors
circuit
decoding circuit
addressing
mos memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7727200A
Other languages
English (en)
Other versions
FR2365179B1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens Corp
Original Assignee
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Corp filed Critical Siemens Corp
Publication of FR2365179A1 publication Critical patent/FR2365179A1/fr
Application granted granted Critical
Publication of FR2365179B1 publication Critical patent/FR2365179B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4082—Address Buffers; level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/02—Shaping pulses by amplifying
    • H03K5/023—Shaping pulses by amplifying using field effect transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)

Abstract

L'invention concerne un dispositif pour réaliser l'adressage d'une mémoire MOS. Ce dispositif est formé d'un circuit décodeur comportant un circuit de pré-décodage VD et par un circuit de post-décodage ND, le circuit VD étant constitué par des étales VDS1 à VDSy raccordés à des amplificateurs d'adresses AVT recevant des signaux d'adresses AO à An, parmi lesquels m signaux sont envoyés à chaque étage VDS (y = n/m), qui comporte 2**m conducteurs de sortie Z aboutissant au circuit de post-décodage ND qui comporte 2**n conducteurs de commande X aboutissant aux cases de mémoire, en sorte que les différents conducteurs X peuvent être sélectionnés respectivement par des combinaisons différentes d'un conducteur de sortie par étage, par l'intermédiaire d'organes de combinaison logique. Application notamment aux modules de mémoires MOS.
FR7727200A 1976-09-15 1977-09-08 Dispositif pour realiser l'adressage d'une memoire mos Granted FR2365179A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2641524A DE2641524B1 (de) 1976-09-15 1976-09-15 Anordnung zur Adressierung eines MOS-Speichers

Publications (2)

Publication Number Publication Date
FR2365179A1 true FR2365179A1 (fr) 1978-04-14
FR2365179B1 FR2365179B1 (fr) 1983-05-13

Family

ID=5987981

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7727200A Granted FR2365179A1 (fr) 1976-09-15 1977-09-08 Dispositif pour realiser l'adressage d'une memoire mos

Country Status (4)

Country Link
JP (1) JPS6032279B2 (fr)
DE (1) DE2641524B1 (fr)
FR (1) FR2365179A1 (fr)
GB (1) GB1588183A (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6413289A (en) * 1988-05-06 1989-01-18 Nec Corp Decoder circuit
KR100206598B1 (ko) * 1995-12-29 1999-07-01 김영환 워드라인 구동 장치
KR101412460B1 (ko) * 2012-05-21 2014-07-01 주식회사 뉴핫맥스 발열 코일의 처짐 방지 구조를 갖는 히터

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3902082A (en) * 1974-02-11 1975-08-26 Mostek Corp Dynamic data input latch and decoder

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3902082A (en) * 1974-02-11 1975-08-26 Mostek Corp Dynamic data input latch and decoder

Also Published As

Publication number Publication date
JPS6032279B2 (ja) 1985-07-26
DE2641524C2 (fr) 1978-07-13
DE2641524B1 (de) 1977-11-17
FR2365179B1 (fr) 1983-05-13
GB1588183A (en) 1981-04-15
JPS5336147A (en) 1978-04-04

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